Inventor · disambiguated record
Rambabu Pyapali
Also filed as: PYAPALI RAMBABU
9 granted patents·1 pending application·69 citations·filing 2000–2011
87Inventor score
Top patents by PatentIndex Score
10 records- 0180US8810280B2Low leakage spare gates for integrated circuitsPYAPALI RAMBABU·Filed 2011·Granted Aug 19, 2014·8 cites·19 claims
- 0276US7890909B2Automatic block composition tool for composing custom blocks having non-standard library cells in an integrated circuit design flowORACLE AMERICA INC·Filed 2008·Granted Feb 15, 2011·16 cites·21 claims
- 0371US7036096B1Estimating capacitances using information including feature sizes extracted from a netlistSUN MICROSYSTEMS INC·Filed 2003·Granted Apr 25, 2006·18 cites·28 claims
- 0469US7007256B2Method and apparatus for power consumption analysis in global netsSUN MICROSYSTEMS INC·Filed 2003·Granted Feb 28, 2006·15 cites·30 claims
- 0552US6954914B2Method and apparatus for signal electromigration analysisSUN MICROSYSTEMS INC·Filed 2003·Granted Oct 11, 2005·5 cites·20 claims
- 0647US7484193B2Method and software for predicting the timing delay of a circuit path using two different timing modelsSUN MICROSYSTEMS INC·Filed 2003·Granted Jan 27, 2009·2 cites·35 claims
- 0745US6596563B2Method for double-layer implementation of metal options in an integrated chip for efficient silicon debugSUN MICROSYSTEMS INC·Filed 2002·Granted Jul 22, 2003·3 cites·15 claims
- 0838US2004049745A1Method and apparatus for waiving noise violationsSUN MICROSYSTEMS INC·Filed 2002·Application pending·0 cites
- 0935US6779131B2Reconfigurable multi-chip modulesSUN MICROSYSTEMS INC·Filed 2001·Granted Aug 17, 2004·2 cites·17 claims
- 1032US6396149B1Method for double-layer implementation of metal options in an integrated chip for efficient silicon debugSUN MICROSYSTEMS INC·Filed 2000·Granted May 28, 2002·0 cites·9 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →