Inventor · disambiguated record
Raj K. Ramanujan
Also filed as: RAMANUJAN RAJ · RAMANUJAN RAJ K
90 granted patents·12 pending applications·1,233 citations·filing 1988–2025
99Inventor score
Files withINTEL CORP63DIGITAL EQUIPMENT CORP9RAMANUJAN RAJ K7QUALCOMM INC4HEWLETT PACKARD DEVELOPMENT CO3
Top patents by PatentIndex Score
102 records- 0197US10241943B2Memory channel that supports near memory and far memory accessINTEL CORP·Filed 2017·Granted Mar 26, 2019·19 cites·17 claims
- 0297US9690493B2Two-level system main memoryINTEL CORP·Filed 2015·Granted Jun 27, 2017·23 cites·61 claims
- 0397US9619408B2Memory channel that supports near memory and far memory accessINTEL CORP·Filed 2016·Granted Apr 11, 2017·30 cites·9 claims
- 0497US9317429B2Apparatus and method for implementing a multi-level memory hierarchy over common memory channelsRAMANUJAN RAJ K·Filed 2011·Granted Apr 19, 2016·92 cites·39 claims
- 0596US12197357B2High performance interconnectINTEL CORP·Filed 2021·Granted Jan 14, 2025·2 cites·20 claims
- 0696US10282323B2Memory channel that supports near memory and far memory accessINTEL CORP·Filed 2018·Granted May 7, 2019·14 cites·4 claims
- 0796US9342453B2Memory channel that supports near memory and far memory accessNALE BILL·Filed 2011·Granted May 17, 2016·80 cites·16 claims
- 0896US9229853B2Method and system for data de-duplicationKHAN JAWAD B·Filed 2011·Granted Jan 5, 2016·70 cites·22 claims
- 0996US8612676B2Two-level system main memoryDAHLEN ERIC J·Filed 2010·Granted Dec 17, 2013·100 cites·20 claims
- 1095US9378142B2Apparatus and method for implementing a multi-level memory hierarchy having different operating modesRAMANUJAN RAJ K·Filed 2011·Granted Jun 28, 2016·27 cites·32 claims
- 1195US9087584B2Two-level system main memoryINTEL CORP·Filed 2013·Granted Jul 21, 2015·23 cites·28 claims
- 1294US10282322B2Memory channel that supports near memory and far memory accessINTEL CORP·Filed 2017·Granted May 7, 2019·14 cites·20 claims
- 1394US9626321B2High performance interconnectINTEL CORP·Filed 2013·Granted Apr 18, 2017·14 cites·1 claims
- 1494US9600416B2Apparatus and method for implementing a multi-level memory hierarchyRAMANUJAN RAJ K·Filed 2011·Granted Mar 21, 2017·23 cites·31 claims
- 1594US9449671B2Techniques for probabilistic dynamic random access memory row repairINTEL CORP·Filed 2013·Granted Sep 20, 2016·20 cites·23 claims
- 1694US8838935B2Apparatus, method, and system for implementing micro page tablesHINTON GLENN·Filed 2010·Granted Sep 16, 2014·79 cites·25 claims
- 1793US10248591B2High performance interconnectINTEL CORP·Filed 2016·Granted Apr 2, 2019·5 cites·23 claims
- 1893US9298606B2Statistical wear leveling for non-volatile system memoryRAMANUJAN RAJ K·Filed 2011·Granted Mar 29, 2016·22 cites·22 claims
- 1992US11741030B2High performance interconnectINTEL CORP·Filed 2020·Granted Aug 29, 2023·2 cites·20 claims
- 2091US9418700B2Bad block management mechanismRAMANUJAN RAJ K·Filed 2012·Granted Aug 16, 2016·15 cites·19 claims
- 2190US11972822B2Programmable ECC for MRAM mixed-read schemeSANDISK TECHNOLOGIES LLC·Filed 2021·Granted Apr 30, 2024·2 cites·19 claims
- 2290US2025321910A1High performance interconnectINTEL CORP·Filed 2025·Application pending·0 cites
- 2389US11200176B2Dynamic partial power down of memory-side cache in a 2-level memory hierarchyINTEL CORP·Filed 2020·Granted Dec 14, 2021·2 cites·12 claims
- 2488US9823849B2Method and apparatus for dynamically allocating storage resources to compute nodesINTEL CORP·Filed 2015·Granted Nov 21, 2017·5 cites·25 claims
- 2587US10102126B2Apparatus and method for implementing a multi-level memory hierarchy having different operating modesINTEL CORP·Filed 2016·Granted Oct 16, 2018·4 cites·20 claims
- 2686US11978491B2Mixed current-forced read scheme for MRAM array with selectorSANDISK TECHNOLOGIES LLC·Filed 2021·Granted May 7, 2024·1 cites·18 claims
- 2786US10691626B2Memory channel that supports near memory and far memory accessINTEL CORP·Filed 2019·Granted Jun 23, 2020·2 cites·14 claims
- 2886US10237169B2Technologies for quality of service based throttling in fabric architecturesINTEL CORP·Filed 2016·Granted Mar 19, 2019·4 cites·14 claims
- 2985US12189550B2High performance interconnectINTEL CORP·Filed 2023·Granted Jan 7, 2025·0 cites·20 claims
- 3085US11216396B2Persistent memory write semantics on PCIe with existing TLP definitionINTEL CORP·Filed 2016·Granted Jan 4, 2022·5 cites·20 claims
- 3185US10146681B2Non-uniform memory access latency adaptations to achieve bandwidth quality of serviceINTEL CORP·Filed 2015·Granted Dec 4, 2018·4 cites·21 claims
- 3284US11138101B2Non-uniform memory access latency adaptations to achieve bandwidth quality of serviceINTEL CORP·Filed 2018·Granted Oct 5, 2021·3 cites·22 claims
- 3384US10095618B2Memory card with volatile and non volatile memory space having multiple usage model configurationsINTEL CORP·Filed 2015·Granted Oct 9, 2018·3 cites·18 claims
- 3483US10365832B2Two-level system main memoryINTEL CORP·Filed 2017·Granted Jul 30, 2019·2 cites·18 claims
- 3582US10996888B2Write credits management for non-volatile memoryQUALCOMM INC·Filed 2018·Granted May 4, 2021·3 cites·27 claims
- 3682US10719443B2Apparatus and method for implementing a multi-level memory hierarchyINTEL CORP·Filed 2019·Granted Jul 21, 2020·2 cites·19 claims
- 3782US9471494B2Method and apparatus for cache line write back operationINTEL CORP·Filed 2013·Granted Oct 18, 2016·7 cites·21 claims
- 3881US8032660B2Apparatus and method for managing subscription requests for a network interface componentINTEL CORP·Filed 2008·Granted Oct 4, 2011·9 cites·18 claims
- 3980US10241912B2Apparatus and method for implementing a multi-level memory hierarchyINTEL CORP·Filed 2017·Granted Mar 26, 2019·2 cites·32 claims
- 4079US11194524B2Apparatus and method for performing persistent write operations using a persistent write commandQUALCOMM INC·Filed 2017·Granted Dec 7, 2021·2 cites·30 claims
- 4179US10102886B2Techniques for probabilistic dynamic random access memory row repairINTEL CORP·Filed 2016·Granted Oct 16, 2018·4 cites·23 claims
- 4278US2025225090A1High performance interconnectINTEL CORP·Filed 2025·Application pending·0 cites
- 4377US10547527B2Apparatus and methods for implementing cluster-wide operational metrics access for coordinated agile schedulingINTEL CORP·Filed 2016·Granted Jan 28, 2020·3 cites·22 claims
- 4477US9286205B2Apparatus and method for phase change memory drift managementRAMANUJAN RAJ K·Filed 2011·Granted Mar 15, 2016·4 cites·21 claims
- 4577US7668997B2High speed bus system that incorporates uni-directional point-to-point busesHEWLETT PACKARD DEVELOPMENT CO·Filed 2005·Granted Feb 23, 2010·6 cites·16 claims
- 4676US9817738B2Clearing poison status on read accesses to volatile memory regions allocated in non-volatile memoryINTEL CORP·Filed 2015·Granted Nov 14, 2017·2 cites·24 claims
- 4776US9129674B2Hybrid memory deviceINTEL CORP·Filed 2013·Granted Sep 8, 2015·5 cites·17 claims
- 4876US5341491AApparatus and method for ensuring that lock requests are serviced in a multiprocessor systemDIGITAL EQUIPMENT CORP·Filed 1993·Granted Aug 23, 1994·67 cites·22 claims
- 4975US11741011B2Memory card with volatile and non volatile memory space having multiple usage model configurationsINTEL CORP·Filed 2022·Granted Aug 29, 2023·0 cites·11 claims
- 5075US11086520B2Method and apparatus for dynamically allocating storage resources to compute nodesINTEL CORP·Filed 2019·Granted Aug 10, 2021·1 cites·25 claims
Showing the top 50 of 102 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →