Inventor · disambiguated record
Ramaswamy Ranganathan
Also filed as: RANGANATHAN RAMASWAMY
20 granted patents·2 pending applications·321 citations·filing 1994–2010
95Inventor score
Top patents by PatentIndex Score
22 records- 0187US6020221AProcess for manufacturing a semiconductor device having a stiffener memberLSI LOGIC CORP·Filed 1996·Granted Feb 1, 2000·128 cites·9 claims
- 0283US8163643B1Enhanced pad design for solder attach devicesOTHIENO MAURICE O·Filed 2010·Granted Apr 24, 2012·12 cites·20 claims
- 0381US6329278B1Multiple row wire bonding with ball bonds of outer bond pads bonded on the leadsLSI LOGIC CORP·Filed 2000·Granted Dec 11, 2001·40 cites·10 claims
- 0473US6798035B1Bonding pad for low k dielectricLSI LOGIC CORP·Filed 2003·Granted Sep 28, 2004·20 cites·20 claims
- 0570US7531442B2Eliminate IMC cracking in post wirebonded dies: macro level stress reduction by modifying dielectric/metal film stack in be layers during Cu/Low-K processingLSI CORP·Filed 2005·Granted May 12, 2009·5 cites·4 claims
- 0670US6825563B1Slotted bonding padLSI LOGIC CORP·Filed 2003·Granted Nov 30, 2004·17 cites·20 claims
- 0770US6743979B1Bonding pad isolationLSI LOGIC CORP·Filed 2003·Granted Jun 1, 2004·16 cites·20 claims
- 0867US6963138B2Dielectric stackLSI LOGIC CORP·Filed 2003·Granted Nov 8, 2005·15 cites·20 claims
- 0964US6573113B1Integrated circuit having dedicated probe pads for use in testing densely patterned bonding padsLSI LOGIC CORP·Filed 2001·Granted Jun 3, 2003·13 cites·11 claims
- 1060US6670214B1Insulated bonding wire for microelectronic packagingLSI LOGIC CORP·Filed 2000·Granted Dec 30, 2003·9 cites·14 claims
- 1150US6781150B2Test structure for detecting bonding-induced cracksLSI LOGIC CORP·Filed 2002·Granted Aug 24, 2004·4 cites·10 claims
- 1250US5385289AEmbedded features for registration measurement in electronics manufacturingDIGITAL EQUIPMENT CORP·Filed 1994·Granted Jan 31, 1995·12 cites·22 claims
- 1349US5457880AEmbedded features for monitoring electronics assembly manufacturing processesDIGITAL EQUIPMENT CORP·Filed 1994·Granted Oct 17, 1995·17 cites·3 claims
- 1446US6998638B2Test structure for detecting bonding-induced cracksLSI LOGIC CORP·Filed 2004·Granted Feb 14, 2006·2 cites·10 claims
- 1542US6861748B2Test structureLSI LOGIC CORP·Filed 2002·Granted Mar 1, 2005·2 cites·10 claims
- 1642US6486002B1Tape design to reduce warpageLSI LOGIC CORP·Filed 2001·Granted Nov 26, 2002·1 cites·5 claims
- 1739US6991147B2Insulated bonding wire tool for microelectronic packagingLSI LOGIC CORP·Filed 2003·Granted Jan 31, 2006·0 cites·5 claims
- 1839US6861343B2Buffer metal layerFiled 2002·Granted Mar 1, 2005·0 cites·20 claims
- 1938US6266249B1Semiconductor flip chip ball grid array packageLSI LOGIC CORP·Filed 1999·Granted Jul 24, 2001·8 cites·21 claims
- 2037US2004178498A1Wire bonding to full array bonding pads on active circuitryFiled 2003·Application pending·0 cites
- 2136US2004070065A1Controlled impedance for wire bonding interconnectsFiled 2002·Application pending·0 cites
- 2230US6425179B1Method for assembling tape ball grid arraysLSI LOGIC CORP·Filed 1999·Granted Jul 30, 2002·0 cites·14 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →