Inventor · disambiguated record
Rahul M. Rao
Also filed as: RAO RAHUL · RAO RAHUL M
45 granted patents·17 pending applications·165 citations·filing 2002–2024
97Inventor score
Top patents by PatentIndex Score
62 records- 0193US7642864B2Circuits and design structures for monitoring NBTI (negative bias temperature instability) effect and/or PBTI (positive bias temperature instability) effectIBM·Filed 2008·Granted Jan 5, 2010·35 cites·20 claims
- 0292US8493774B2Performing logic functions on more than one memory cell within an array of memory cellsKUANG JENTE B·Filed 2011·Granted Jul 23, 2013·28 cites·20 claims
- 0387US9697306B1Formal verification driven power modeling and design verificationIBM·Filed 2016·Granted Jul 4, 2017·4 cites·1 claims
- 0487US9460251B1Formal verification driven power modeling and design verificationIBM·Filed 2016·Granted Oct 4, 2016·4 cites·1 claims
- 0584US8456247B2Monitoring negative bias temperature instability (NBTI) and/or positive bias temperature instability (PBTI)KIM JAE-JOON·Filed 2011·Granted Jun 4, 2013·9 cites·16 claims
- 0683US10933471B2Method for continuous and controllable production of single walled carbon nanotubesHONDA MOTOR CO LTD·Filed 2018·Granted Mar 2, 2021·1 cites·16 claims
- 0781US7439755B2Electronic circuit for measurement of transistor variability and the likeIBM·Filed 2007·Granted Oct 21, 2008·8 cites·14 claims
- 0879US7550987B2Method and circuit for measuring operating and leakage current of individual blocks within an array of test circuit blocksIBM·Filed 2007·Granted Jun 23, 2009·10 cites·20 claims
- 0978US7088141B2Multi-threshold complementary metal-oxide semiconductor (MTCMOS) bus circuit and method for reducing bus power consumption via pulsed standby switchingIBM·Filed 2004·Granted Aug 8, 2006·21 cites·20 claims
- 1075US11507721B2Scan chain wirelength optimization using Q-learning based reinforcement learningIBM·Filed 2020·Granted Nov 22, 2022·1 cites·17 claims
- 1174US9280630B1Modified standard cells to address fast pathsIBM·Filed 2014·Granted Mar 8, 2016·5 cites·14 claims
- 1274US9064071B2Usage-based temporal degradation estimation for memory elementsBANSAL ADITYA·Filed 2011·Granted Jun 23, 2015·3 cites·12 claims
- 1373US11036905B1Hierarchical power analysis using improved activity abstraction and capacitance abstraction by accounting for design heterogeneity extremitiesIBM·Filed 2020·Granted Jun 15, 2021·1 cites·20 claims
- 1473US9643847B2Method for growth of vertically aligned carbon nanotubes on diamond substratesHONDA MOTOR CO LTD·Filed 2014·Granted May 9, 2017·1 cites·15 claims
- 1572US8966420B2Estimating delay deterioration due to device degradation in integrated circuitsBANSAL ADITYA·Filed 2012·Granted Feb 24, 2015·2 cites·10 claims
- 1672US8139400B2Enhanced static random access memory stability using asymmetric access transistors and design structure for sameBANSAL ADITYA·Filed 2008·Granted Mar 20, 2012·7 cites·15 claims
- 1769US10955900B2Speculation throttling for reliability managementIBM·Filed 2018·Granted Mar 23, 2021·1 cites·17 claims
- 1866US8004305B2Electronic circuit for measurement of transistor variability and the likeIBM·Filed 2009·Granted Aug 23, 2011·3 cites·7 claims
- 1964US7495969B2Techniques for improving write stability of memory with decoupled read and write bit linesIBM·Filed 2007·Granted Feb 24, 2009·4 cites·9 claims
- 2061US6791361B2Technique for mitigating gate leakage during a sleep stateIBM·Filed 2002·Granted Sep 14, 2004·7 cites·12 claims
- 2160US10354028B2Formal verification driven power modeling and design verificationIBM·Filed 2017·Granted Jul 16, 2019·0 cites·1 claims
- 2260US7764080B2Methods of operating an electronic circuit for measurement of transistor variability and the likeIBM·Filed 2008·Granted Jul 27, 2010·2 cites·14 claims
- 2360US7746709B2Memory circuit with decoupled read and write bit lines and improved write stabilityIBM·Filed 2008·Granted Jun 29, 2010·3 cites·12 claims
- 2460US2018232469A1On the fly netlist compression in power analysisIBM·Filed 2018·Application pending·0 cites
- 2560US2018232470A1Fly netlist compression in power analysisIBM·Filed 2018·Application pending·0 cites
- 2658US9996649B2On the fly netlist compression in power analysisIBM·Filed 2016·Granted Jun 12, 2018·0 cites·1 claims
- 2758US2025237691A1Interconnect process monitor for assessing wire parasitics across configurationsIBM·Filed 2024·Application pending·0 cites
- 2857US11928409B2Dynamic abstract generation and synthesis flow with area predictionIBM·Filed 2022·Granted Mar 12, 2024·0 cites·20 claims
- 2957US11922109B2Predictive antenna diode insertionIBM·Filed 2021·Granted Mar 5, 2024·0 cites·20 claims
- 3057US10002220B2On the fly netlist compression in power analysisIBM·Filed 2016·Granted Jun 19, 2018·0 cites·20 claims
- 3157US9519746B1Addressing early mode slack fails by book decompositionIBM·Filed 2015·Granted Dec 13, 2016·1 cites·20 claims
- 3256US10216878B2Cross-current power modelling using logic simulationIBM·Filed 2017·Granted Feb 26, 2019·0 cites·1 claims
- 3356US10007747B2Cross-current power modelling using logic simulationIBM·Filed 2017·Granted Jun 26, 2018·0 cites·1 claims
- 3456US7548822B2Apparatus and method for determining the slew rate of a signal produced by an integrated circuitIBM·Filed 2007·Granted Jun 16, 2009·2 cites·7 claims
- 3555US2017235856A1Formal verification driven power modeling and design verificationIBM·Filed 2016·Application pending·0 cites
- 3655US2025232103A1Power modeled integrated circuitIBM·Filed 2024·Application pending·0 cites
- 3755US2015154331A1Estimating delay deterioration due to device degradation in integrated circuitsIBM·Filed 2015·Application pending·0 cites
- 3854US10990443B2Utilization profiling and scheduling operations using thread specific execution units usage of a multi-core multi-threaded processorIBM·Filed 2018·Granted Apr 27, 2021·0 cites·15 claims
- 3953US11999568B2Mobile robot interactions independent of localization dataHDS MERCURY INC·Filed 2020·Granted Jun 4, 2024·0 cites·20 claims
- 4053US9916406B2Cross-current power modelling using logic simulationIBM·Filed 2016·Granted Mar 13, 2018·0 cites·1 claims
- 4153US7241479B2Thermal CVD synthesis of nanostructuresUNIV CLEMSON·Filed 2003·Granted Jul 10, 2007·2 cites·37 claims
- 4253US2024386175A1Timing analysis for non-scan latchesIBM·Filed 2023·Application pending·0 cites
- 4352US10920085B2Alteration of carbon fiber surface properties via growing of carbon nanotubesHONDA MOTOR CO LTD·Filed 2016·Granted Feb 16, 2021·0 cites·17 claims
- 4452US9754058B2Cross-current power modelling using logic simulationIBM·Filed 2015·Granted Sep 5, 2017·0 cites·20 claims
- 4551US9058448B2Usage-based temporal degradation estimation for memory elementsBANSAL ADITYA·Filed 2012·Granted Jun 16, 2015·0 cites·13 claims
- 4651US2013253868A1Estimating delay deterioration due to device degradation in integrated circuitsBANSAL ADITYA·Filed 2012·Application pending·0 cites
- 4750US2025036188A1Power reduction by removal of redundancy in clock pathways of vlsi circuitsIBM·Filed 2023·Application pending·0 cites
- 4849US11947891B2Balancing cycle stealing with early mode violationsIBM·Filed 2021·Granted Apr 2, 2024·0 cites·20 claims
- 4949US2024165802A1System and Method for Scheduling Tasks for Mobile RobotsZEBRA TECH CORP·Filed 2022·Application pending·0 cites
- 5047US12261165B2Electronic circuits including hybrid voltage threshold logical entitiesIBM·Filed 2021·Granted Mar 25, 2025·0 cites·14 claims
Showing the top 50 of 62 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →