Inventor · disambiguated record
Rajesh Rengarajan
Also filed as: RENGARAJAN RAJESH
27 granted patents·3 pending applications·582 citations·filing 1997–2012
97Inventor score
Top patents by PatentIndex Score
30 records- 0190US6869866B1Silicide proximity structures for CMOS device performance improvementsIBM·Filed 2003·Granted Mar 22, 2005·53 cites·23 claims
- 0290US6635526B1Structure and method for dual work function logic devices in vertical DRAM processINFINEON TECHNOLOGIES AG·Filed 2002·Granted Oct 21, 2003·57 cites·20 claims
- 0388US5940717ARecessed shallow trench isolation structure nitride liner and method for making sameSIEMENS AG·Filed 1998·Granted Aug 17, 1999·81 cites·12 claims
- 0487US6501131B1Transistors having independently adjustable parametersIBM·Filed 1999·Granted Dec 31, 2002·95 cites·15 claims
- 0585US9355887B2Dual trench isolation for CMOS with hybrid orientationsCHAN VICTOR·Filed 2012·Granted May 31, 2016·6 cites·11 claims
- 0682US6740920B2Vertical MOSFET with horizontally graded channel dopingIBM·Filed 2002·Granted May 25, 2004·27 cites·6 claims
- 0779US6521493B1Semiconductor device with STI sidewall implantIBM·Filed 2000·Granted Feb 18, 2003·28 cites·24 claims
- 0872US6329704B1Ultra-shallow junction dopant layer having a peak concentration within a dielectric layerIBM·Filed 1999·Granted Dec 11, 2001·34 cites·7 claims
- 0971US6323103B1Method for fabricating transistorsSIEMENS AG·Filed 1998·Granted Nov 27, 2001·39 cites·41 claims
- 1070US6194278B1Device performance by employing an improved method for forming halo implantsINFINEON TECHNOLOGIES CORP·Filed 1999·Granted Feb 27, 2001·36 cites·21 claims
- 1168US6724053B1PMOSFET device with localized nitrogen sidewall implantationIBM·Filed 2000·Granted Apr 20, 2004·12 cites·9 claims
- 1266US8097516B2Dual trench isolation for CMOS with hybrid orientationsCHAN VICTOR·Filed 2008·Granted Jan 17, 2012·2 cites·6 claims
- 1365US6960523B2Method of reducing erosion of a nitride gate cap layer during reactive ion etch of nitride liner layer for bit line contact of DRAM deviceIBM·Filed 2003·Granted Nov 1, 2005·10 cites·15 claims
- 1464US7572689B2Method and structure for reducing induced mechanical stressesIBM·Filed 2007·Granted Aug 11, 2009·2 cites·2 claims
- 1562US6960818B1Recessed shallow trench isolation structure nitride liner and method for making sameSIEMENS AG·Filed 1997·Granted Nov 1, 2005·24 cites·8 claims
- 1662US6127215ADeep pivot mask for enhanced buried-channel PFET performance and reliabilityIBM·Filed 1998·Granted Oct 3, 2000·23 cites·20 claims
- 1761US7314790B2Enhancement of electron and hole mobilities in <110> Si under biaxial compressive strainIBM·Filed 2006·Granted Jan 1, 2008·1 cites·15 claims
- 1860US6426247B1Low bitline capacitance structure and method of making sameIBM·Filed 2001·Granted Jul 30, 2002·9 cites·10 claims
- 1960US6387782B2Process of forming an ultra-shallow junction dopant layer having a peak concentration within a dielectric layerIBM·Filed 2001·Granted May 14, 2002·6 cites·15 claims
- 2057US7473607B2Method of manufacturing a multi-workfunction gates for a CMOS circuitIBM·Filed 2005·Granted Jan 6, 2009·1 cites·13 claims
- 2155US6197632B1Method for dual sidewall oxidation in high density, high performance DRAMSIBM·Filed 1999·Granted Mar 6, 2001·14 cites·12 claims
- 2254US7943486B2Enhancement of electron and hole mobilities in <110> Si under biaxial compressive strainIBM·Filed 2008·Granted May 17, 2011·0 cites·11 claims
- 2354US6074903AMethod for forming electrical isolation for semiconductor devicesSIEMENS AG·Filed 1998·Granted Jun 13, 2000·19 cites·11 claims
- 2453US7883948B2Method and structure for reducing induced mechanical stressesIBM·Filed 2009·Granted Feb 8, 2011·0 cites·17 claims
- 2553US7462525B2Enhancement of electron and hole mobilities in <110> Si under biaxial compressive strainIBM·Filed 2007·Granted Dec 9, 2008·0 cites·10 claims
- 2653US2008036028A1Dual trench isolation for cmos with hybrid orientationsIBM·Filed 2007·Application pending·0 cites
- 2749US7161169B2Enhancement of electron and hole mobilities in <110> Si under biaxial compressive strainIBM·Filed 2004·Granted Jan 9, 2007·2 cites·7 claims
- 2849US2007040235A1Dual trench isolation for CMOS with hybrid orientationsIBM·Filed 2005·Application pending·0 cites
- 2941US6867087B2Formation of dual work function gate electrodeINFINEON TECHNOLOGIES AG·Filed 2001·Granted Mar 15, 2005·1 cites·12 claims
- 3033US2002177264A1Reducing threshold voltage roll-up/roll-off effect for MOSFETSIBM·Filed 2001·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →