Inventor · disambiguated record
Ravi P. Singh
Also filed as: SINGH RAVI · SINGH RAVI P · SINGH RAVI PRATAP
48 granted patents·5 pending applications·442 citations·filing 2000–2024
98Inventor score
Top patents by PatentIndex Score
53 records- 0193US11704067B2Performing multiple point table lookups in a single cycle in a system on chipNVIDIA CORP·Filed 2021·Granted Jul 18, 2023·6 cites·20 claims
- 0293US11593290B1Using a hardware sequencer in a direct memory access system of a system on a chipNVIDIA CORP·Filed 2021·Granted Feb 28, 2023·4 cites·20 claims
- 0393US11573921B1Built-in self-test for a programmable vision accelerator of a system on a chipNVIDIA CORP·Filed 2021·Granted Feb 7, 2023·5 cites·20 claims
- 0493US11573795B1Using a vector processor to configure a direct memory access system for feature tracking operations in a system on a chipNVIDIA CORP·Filed 2021·Granted Feb 7, 2023·6 cites·20 claims
- 0592US11636063B2Hardware accelerated anomaly detection using a min/max collector in a system on a chipNVIDIA CORP·Filed 2021·Granted Apr 25, 2023·5 cites·20 claims
- 0690US7028165B2Processor stallingANALOG DEVICES INC·Filed 2000·Granted Apr 11, 2006·66 cites·30 claims
- 0790US6823448B2Exception handling using an exception pipeline in a pipelined processorINTEL CORP·Filed 2000·Granted Nov 23, 2004·69 cites·25 claims
- 0888US11934829B2Using a vector processor to configure a direct memory access system for feature tracking operations in a system on a chipNVIDIA CORP·Filed 2022·Granted Mar 19, 2024·1 cites·20 claims
- 0988US6754808B1Valid bit generation and tracking in a pipelined processorINTEL CORP·Filed 2000·Granted Jun 22, 2004·51 cites·26 claims
- 1087US12093539B2Using per memory bank load caches for reducing power use in a system on a chipNVIDIA CORP·Filed 2022·Granted Sep 17, 2024·1 cites·20 claims
- 1182US11630800B2Programmable vision acceleratorNVIDIA CORP·Filed 2016·Granted Apr 18, 2023·5 cites·21 claims
- 1281US11836527B2Accelerating table lookups using a decoupled lookup table accelerator in a system on a chipNVIDIA CORP·Filed 2021·Granted Dec 5, 2023·1 cites·20 claims
- 1381US11593001B1Using per memory bank load caches for reducing power use in a system on a chipNVIDIA CORP·Filed 2021·Granted Feb 28, 2023·1 cites·20 claims
- 1478US6986026B2Single-step processing and selecting debugging modesANALOG DEVICES INC·Filed 2000·Granted Jan 10, 2006·31 cites·8 claims
- 1577US2025103529A1Using a hardware sequencer in a direct memory access system of a system on a chipNVIDIA CORP·Filed 2024·Application pending·0 cites
- 1675US7272705B2Early exception detectionANALOG DEVICES INC·Filed 2005·Granted Sep 18, 2007·6 cites·12 claims
- 1774US6748523B1Hardware loopsINTEL CORP·Filed 2000·Granted Jun 8, 2004·19 cites·43 claims
- 1873US12204475B2Using a hardware sequencer in a direct memory access system of a system on a chipNVIDIA CORP·Filed 2022·Granted Jan 21, 2025·0 cites·20 claims
- 1973US7266676B2Method and apparatus for branch prediction based on branch targets utilizing tag and data arraysANALOG DEVICES INC·Filed 2003·Granted Sep 4, 2007·23 cites·30 claims
- 2073US6665795B1Resetting a programmable processorINTEL CORP·Filed 2000·Granted Dec 16, 2003·18 cites·45 claims
- 2173US2024134645A1Using a vector processor to configure a direct memory access system for feature tracking operations in a system on a chipNVIDIA CORP·Filed 2024·Application pending·0 cites
- 2270US12050548B2Built-in self-test for a programmable vision accelerator of a system on a chipNVIDIA CORP·Filed 2022·Granted Jul 30, 2024·0 cites·20 claims
- 2370US11940947B2Hardware accelerated anomaly detection using a min/max collector in a system on a chipNVIDIA CORP·Filed 2023·Granted Mar 26, 2024·0 cites·20 claims
- 2470US6898693B1Hardware loopsANALOG DEVICES INC·Filed 2000·Granted May 24, 2005·15 cites·75 claims
- 2567US7155570B1FIFO write/LIFO read trace buffer with software and hardware loop compressionANALOG DEVICES INC·Filed 2000·Granted Dec 26, 2006·13 cites·30 claims
- 2666US6766444B1Hardware loopsINTEL CORP·Filed 2000·Granted Jul 20, 2004·11 cites·26 claims
- 2765US7168032B2Data synchronization for a test access portANALOG DEVICES INC·Filed 2000·Granted Jan 23, 2007·10 cites·23 claims
- 2863US6842812B1Event handlingINTEL CORP·Filed 2000·Granted Jan 11, 2005·9 cites·27 claims
- 2962US6976151B1Decoding an instruction portion and forwarding part of the portion to a first destination, re-encoding a different part of the portion and forwarding to a second destinationANALOG DEVICES INC·Filed 2000·Granted Dec 13, 2005·8 cites·15 claims
- 3062US6670895B2Method and apparatus for swapping the contents of address registersANALOG DEVICES INC·Filed 2002·Granted Dec 30, 2003·8 cites·25 claims
- 3161US6681273B1High performance, variable data width FIFO bufferANALOG DEVICES INC·Filed 2000·Granted Jan 20, 2004·11 cites·38 claims
- 3260US6920515B2Early exception detectionANALOG DEVICES INC·Filed 2001·Granted Jul 19, 2005·6 cites·12 claims
- 3358US7360059B2Variable width alignment engine for aligning instructions based on transition between buffersANALOG DEVICES INC·Filed 2006·Granted Apr 15, 2008·1 cites·18 claims
- 3457US6789184B1Instruction address generation and tracking in a pipelined processorINTEL CORP·Filed 2000·Granted Sep 7, 2004·5 cites·20 claims
- 3555US7082516B1Aligning instructions using a variable width alignment engine having an intelligent buffer refill mechanismANALOG DEVICES INC·Filed 2000·Granted Jul 25, 2006·4 cites·12 claims
- 3655US7069420B1Decode and dispatch of multi-issue and multiple width instructionsANALOG DEVICES INC·Filed 2000·Granted Jun 27, 2006·4 cites·18 claims
- 3755US7065636B2Hardware loops and pipeline system using advanced generation of loop parametersANALOG DEVICES INC·Filed 2000·Granted Jun 20, 2006·4 cites·29 claims
- 3855US6728870B1Register move operationsINTEL CORP·Filed 2000·Granted Apr 27, 2004·4 cites·13 claims
- 3954US6829701B2Watchpoint engine for a pipelined processorINTEL CORP·Filed 2000·Granted Dec 7, 2004·4 cites·8 claims
- 4053US7366876B1Efficient emulation instruction dispatch based on instruction widthANALOG DEVICES INC·Filed 2000·Granted Apr 29, 2008·3 cites·23 claims
- 4152US12118353B2Performing load and permute with a single instruction in a system on a chipNVIDIA CORP·Filed 2021·Granted Oct 15, 2024·0 cites·20 claims
- 4252US12099439B2Performing load and store operations of 2D arrays in a single cycle in a system on a chipNVIDIA CORP·Filed 2021·Granted Sep 24, 2024·0 cites·20 claims
- 4352US7043582B2Self-nesting interruptsANALOG DEVICES INC·Filed 2002·Granted May 9, 2006·2 cites·27 claims
- 4450US11954496B2Reduced memory write requirements in a system on a chip using automatic store predicationNVIDIA CORP·Filed 2021·Granted Apr 9, 2024·0 cites·20 claims
- 4550US7472259B2Multi-cycle instructionsANALOG DEVICES INC·Filed 2000·Granted Dec 30, 2008·1 cites·37 claims
- 4650US6920547B2Register adjustment based on adjustment values determined at multiple stages within a pipeline of a processorANALOG DEVICES INC·Filed 2000·Granted Jul 19, 2005·1 cites·19 claims
- 4747US7036000B2Valid bit generation and tracking in a pipelined processorANALOG DEVICES INC·Filed 2004·Granted Apr 25, 2006·0 cites·11 claims
- 4843US6763453B2Security on hardware loopsINTEL CORP·Filed 2000·Granted Jul 13, 2004·0 cites·46 claims
- 4943US2023130478A1Hybrid solution for stereo imagingNVIDIA CORP·Filed 2020·Application pending·0 cites
- 5043US2023050062A1Simd data path organization to increase processing throughput in a system on a chipNVIDIA CORP·Filed 2021·Application pending·0 cites
Showing the top 50 of 53 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →