Inventor · disambiguated record
Ramakrishna K. Tanikella
Also filed as: TANIKELLA RAMAKRISHNA K · TANIKELLA RAMAKRISHNA KISHORE
17 granted patents·203 citations·filing 2003–2019
94Inventor score
Top patents by PatentIndex Score
17 records- 0194US10804255B1Circuit for and method of transmitting a signal in an integrated circuit deviceXILINX INC·Filed 2019·Granted Oct 13, 2020·14 cites·20 claims
- 0294US7061271B1Six-input look-up table for use in a field programmable gate arrayXILINX INC·Filed 2004·Granted Jun 13, 2006·58 cites·16 claims
- 0391US9054684B1Single event upset enhanced architectureXILINX INC·Filed 2013·Granted Jun 9, 2015·12 cites·7 claims
- 0491US7312631B1Structures and methods for avoiding hold time violations in a programmable logic deviceXILINX INC·Filed 2005·Granted Dec 25, 2007·18 cites·8 claims
- 0590US8001511B1Methods of implementing and modeling interconnect lines at optional boundaries in multi-product programmable IC diesXILINX INC·Filed 2008·Granted Aug 16, 2011·16 cites·9 claims
- 0688US8933447B1Method and apparatus for programmable device testing in stacked die applicationsRAHMAN ARIFUR·Filed 2010·Granted Jan 13, 2015·10 cites·15 claims
- 0784US7451421B1Methods of implementing and modeling interconnect lines at optional boundaries in multi-product programmable IC diesXILINX INC·Filed 2006·Granted Nov 11, 2008·12 cites·8 claims
- 0882US7548089B1Structures and methods to avoiding hold time violations in a programmable logic deviceXILINX INC·Filed 2007·Granted Jun 16, 2009·10 cites·6 claims
- 0980US7199610B1Integrated circuit interconnect structure having reduced coupling between interconnect linesXILINX INC·Filed 2005·Granted Apr 3, 2007·11 cites·20 claims
- 1078US10998904B1Programmable termination circuits for programmable devicesXILINX INC·Filed 2019·Granted May 4, 2021·2 cites·16 claims
- 1177US10503861B1Placing and routing an interface portion and a main portion of a circuit designXILINX INC·Filed 2018·Granted Dec 10, 2019·3 cites·20 claims
- 1276US7743175B1Methods of initializing routing structures in integrated circuitsXILINX INC·Filed 2008·Granted Jun 22, 2010·7 cites·18 claims
- 1373US9000529B1Reduction of single event upsets within a semiconductor integrated circuitXILINX INC·Filed 2012·Granted Apr 7, 2015·3 cites·18 claims
- 1471US7075332B1Six-input look-up table and associated memory control circuitry for use in a field programmable gate arrayXILINX INC·Filed 2004·Granted Jul 11, 2006·14 cites·11 claims
- 1564US6933747B1Structures and methods of testing interconnect structures in programmable logic devicesXILINX INC·Filed 2003·Granted Aug 23, 2005·10 cites·31 claims
- 1656US7382157B1Interconnect driver circuits for dynamic logicXILINX INC·Filed 2006·Granted Jun 3, 2008·2 cites·17 claims
- 1748US8120382B2Programmable integrated circuit with mirrored interconnect structureBAUER TREVOR J·Filed 2010·Granted Feb 21, 2012·1 cites·20 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →