Inventor · disambiguated record
Ralph D. Wittig
Also filed as: WITTIG RALPH · WITTIG RALPH D · WITTIG RALPH DETLEF
56 granted patents·4 pending applications·2,498 citations·filing 1997–2023
99Inventor score
Files withXILINX INC52ADVANCED MICRO DEVICES INC2JAMES-ROXBY PHILIP B2BALLANTYNE RICHARD S1CARRILLO JORGE ERNESTO1
Top patents by PatentIndex Score
60 records- 0199US6150839ARapidly reconfigurable FPGA having a multiple region architecture with reconfiguration caches useable as data RAMXILINX INC·Filed 2000·Granted Nov 21, 2000·183 cites·5 claims
- 0299US6150838AFPGA configurable logic block with multi-purpose logic/memory circuitXILINX INC·Filed 1999·Granted Nov 21, 2000·315 cites·37 claims
- 0399US6091263ARapidly reconfigurable FPGA having a multiple region architecture with reconfiguration caches useable as data RAMXILINX INC·Filed 1997·Granted Jul 18, 2000·412 cites·37 claims
- 0498US6396302B2Configurable logic element with expander structuresXILINX INC·Filed 2001·Granted May 28, 2002·92 cites·15 claims
- 0597US10802807B1Control and reconfiguration of data flow graphs on heterogeneous computing platformXILINX INC·Filed 2019·Granted Oct 13, 2020·25 cites·20 claims
- 0696US11281440B1Control and reconfiguration of data flow graphs on heterogeneous computing platformXILINX INC·Filed 2020·Granted Mar 22, 2022·5 cites·20 claims
- 0796US10866753B2Data processing engine arrangement in a deviceXILINX INC·Filed 2018·Granted Dec 15, 2020·15 cites·10 claims
- 0896US10747690B2Device with data processing engine arrayXILINX INC·Filed 2018·Granted Aug 18, 2020·19 cites·20 claims
- 0996US6388466B1FPGA logic element with variable-length shift register capabilityXILINX INC·Filed 2001·Granted May 14, 2002·92 cites·30 claims
- 1095US9218443B1Heterogeneous multiprocessor program compilation targeting programmable integrated circuitsXILINX INC·Filed 2014·Granted Dec 22, 2015·59 cites·20 claims
- 1195US6457164B1Hetergeneous method for determining module placement in FPGAsXILINX INC·Filed 2000·Granted Sep 24, 2002·103 cites·17 claims
- 1295US6400180B2Configurable lookup table for programmable logic devicesXILINX INC·Filed 2001·Granted Jun 4, 2002·71 cites·9 claims
- 1395US6208163B1FPGA configurable logic block with multi-purpose logic/memory circuitXILINX INC·Filed 1999·Granted Mar 27, 2001·87 cites·11 claims
- 1495US6118300AMethod for implementing large multiplexers with FPGA lookup tablesXILINX INC·Filed 1998·Granted Sep 12, 2000·102 cites·15 claims
- 1594US6501296B2Logic/memory circuit having a plurality of operating modesXILINX INC·Filed 2001·Granted Dec 31, 2002·47 cites·24 claims
- 1693US8443230B1Methods and systems with transaction-level lockstepJAMES-ROXBY PHILIP B·Filed 2010·Granted May 14, 2013·44 cites·20 claims
- 1793US6191610B1Method for implementing large multiplexers with FPGA lookup tablesXILINX INC·Filed 2000·Granted Feb 20, 2001·46 cites·2 claims
- 1890US7721090B1Event-driven simulation of IP using third party event-driven simulatorsXILINX INC·Filed 2006·Granted May 18, 2010·28 cites·19 claims
- 1988US6583645B1Field programmable optical arraysXILINX INC·Filed 2001·Granted Jun 24, 2003·38 cites·4 claims
- 2088US6184712B1FPGA configurable logic block with multi-purpose logic/memory circuitXILINX INC·Filed 1999·Granted Feb 6, 2001·60 cites·10 claims
- 2187US11204745B2Dataflow graph programming environment for a heterogenous processing systemXILINX INC·Filed 2019·Granted Dec 21, 2021·4 cites·18 claims
- 2287US6803786B1Structures and methods providing columns of tightly coupled processor and RAM blocks within an array of logic blocksXILINX INC·Filed 2003·Granted Oct 12, 2004·26 cites·20 claims
- 2386US8447957B1Coprocessor interface architecture and methods of operating the sameCARRILLO JORGE ERNESTO·Filed 2006·Granted May 21, 2013·32 cites·18 claims
- 2486US6847229B2Configurable logic element with expander structuresXILINX INC·Filed 2003·Granted Jan 25, 2005·20 cites·13 claims
- 2585US10990552B1Streaming interconnect architecture for data processing engine arrayXILINX INC·Filed 2018·Granted Apr 27, 2021·4 cites·20 claims
- 2685US6505337B1Method for implementing large multiplexers with FPGA lookup tablesXILINX INC·Filed 2000·Granted Jan 7, 2003·29 cites·10 claims
- 2784US10860766B1Compilation flow for a heterogeneous multi-core architectureXILINX INC·Filed 2019·Granted Dec 8, 2020·4 cites·20 claims
- 2884US8479042B1Transaction-level lockstepJAMES-ROXBY PHILIP B·Filed 2010·Granted Jul 2, 2013·8 cites·20 claims
- 2983US11573726B1Data processing engine arrangement in a deviceXILINX INC·Filed 2020·Granted Feb 7, 2023·1 cites·8 claims
- 3082US7248073B2Configurable logic element with expander structuresXILINX INC·Filed 2006·Granted Jul 24, 2007·7 cites·10 claims
- 3182US6216258B1FPGA modules parameterized by expressionsXILINX INC·Filed 1998·Granted Apr 10, 2001·84 cites·20 claims
- 3280US6292925B1Context-sensitive self implementing modulesXILINX INC·Filed 1998·Granted Sep 18, 2001·90 cites·37 claims
- 3378US10824434B1Dynamically structured single instruction, multiple data (SIMD) instructionsXILINX INC·Filed 2018·Granted Nov 3, 2020·2 cites·20 claims
- 3478US7948269B1System and method for open drain/open collector structures in an integrated circuitXILINX INC·Filed 2009·Granted May 24, 2011·10 cites·19 claims
- 3578US6630841B2Configurable logic element with expander structuresXILINX INC·Filed 2002·Granted Oct 7, 2003·14 cites·20 claims
- 3678US6243851B1Heterogeneous method for determining module placement in FPGAsXILINX INC·Filed 1998·Granted Jun 5, 2001·71 cites·30 claims
- 3777US11972132B2Data processing engine arrangement in a deviceXILINX INC·Filed 2022·Granted Apr 30, 2024·0 cites·19 claims
- 3876US9846660B2Heterogeneous multiprocessor platform targeting programmable integrated circuitsXILINX INC·Filed 2014·Granted Dec 19, 2017·5 cites·20 claims
- 3976US6603332B2Configurable logic block for PLD with logic gate for combining output with another configurable logic blockXILINX INC·Filed 2001·Granted Aug 5, 2003·17 cites·16 claims
- 4075US6260182B1Method for specifying routing in a logic module by direct module communicationXILINX INC·Filed 1998·Granted Jul 10, 2001·70 cites·32 claims
- 4174US7181718B1Structures and methods providing columns of tightly coupled processor and RAM blocks within an array of logic blocksXILINX INC·Filed 2004·Granted Feb 20, 2007·13 cites·29 claims
- 4274US6288569B1Memory array with hard and soft decodersXILINX INC·Filed 2000·Granted Sep 11, 2001·12 cites·14 claims
- 4373US7243330B1Method and apparatus for providing self-implementing hardware-software librariesXILINX INC·Filed 2005·Granted Jul 10, 2007·8 cites·15 claims
- 4472US11687327B2Control and reconfiguration of data flow graphs on heterogeneous computing platformXILINX INC·Filed 2022·Granted Jun 27, 2023·0 cites·20 claims
- 4571US7111273B1Softpal implementation and mapping technology for FPGAs with dedicated resourcesXILINX INC·Filed 2003·Granted Sep 19, 2006·16 cites·43 claims
- 4666US7310594B1Method and system for designing a multiprocessorXILINX INC·Filed 2002·Granted Dec 18, 2007·13 cites·24 claims
- 4765US7340585B1Method and system for fast linked processor in a system on a chip (SoC)XILINX INC·Filed 2002·Granted Mar 4, 2008·12 cites·19 claims
- 4863US6259205B1High-pressure discharge lamp with a discharge vessel having conical of concentric endsPHILIPS CORP·Filed 1998·Granted Jul 10, 2001·17 cites·5 claims
- 4963US2022058005A1Dataflow graph programming environment for a heterogenous processing systemXILINX INC·Filed 2021·Application pending·0 cites
- 5062US6237129B1Method for constraining circuit element positions in structured layoutsXILINX INC·Filed 1998·Granted May 22, 2001·34 cites·35 claims
Showing the top 50 of 60 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →