Inventor · disambiguated record
Reken Patel
Also filed as: PATEL REKEN
11 granted patents·9 pending applications·6 citations·filing 2011–2024
81Inventor score
Top patents by PatentIndex Score
20 records- 0186US11145541B2Conductive via and metal line end fabrication and structures resulting therefromINTEL CORP·Filed 2017·Granted Oct 12, 2021·5 cites·18 claims
- 0275US12369392B2Fabrication of gate-all-around integrated circuit structures having pre-spacer deposition cut gatesINTEL CORP·Filed 2024·Granted Jul 22, 2025·0 cites·20 claims
- 0375US2025046713A1Self-aligned patterning with colored blocking and structures resulting therefromINTEL CORP·Filed 2024·Application pending·0 cites
- 0473US12080639B2Contact over active gate structures with metal oxide layers to inhibit shortingINTEL CORP·Filed 2019·Granted Sep 3, 2024·1 cites·17 claims
- 0572US11972979B21D vertical edge blocking (VEB) via and plugINTEL CORP·Filed 2023·Granted Apr 30, 2024·0 cites·22 claims
- 0664US12400913B2Contact over active gate structures with conductive trench contact taps for advanced integrated circuit structure fabricationINTEL CORP·Filed 2021·Granted Aug 26, 2025·0 cites·20 claims
- 0761US11990472B2Fabrication of gate-all-around integrated circuit structures having pre-spacer deposition cut gatesINTEL CORP·Filed 2020·Granted May 21, 2024·0 cites·11 claims
- 0859US11652045B2Via contact patterning method to increase edge placement error marginINTEL CORP·Filed 2021·Granted May 16, 2023·0 cites·20 claims
- 0958US12154855B2Self-aligned patterning with colored blocking and structures resulting therefromINTEL CORP·Filed 2019·Granted Nov 26, 2024·0 cites·16 claims
- 1055US11721580B21D vertical edge blocking (VEB) via and plugINTEL CORP·Filed 2019·Granted Aug 8, 2023·0 cites·11 claims
- 1155US2022406778A1Integrated circuit structures having plugged metal gatesINTEL CORP·Filed 2021·Application pending·0 cites
- 1254US2025089228A1Gate contact patterning for static random-access memoryINTEL CORP·Filed 2023·Application pending·0 cites
- 1352US11211324B2Via contact patterning method to increase edge placement error marginINTEL CORP·Filed 2019·Granted Dec 28, 2021·0 cites·20 claims
- 1450US2024332071A1Plasma enhanced atomic layer deposition of dielectric material upon oxidizable materialINTEL CORP·Filed 2023·Application pending·0 cites
- 1550US2024113177A1Stacked source or drain contact flyoverINTEL CORP·Filed 2022·Application pending·0 cites
- 1650US2023320057A1Recessed transistor terminal via jumpersINTEL CORP·Filed 2022·Application pending·0 cites
- 1749US2025006733A1Integrated circuit structures with differential epitaxial source or drain dentINTEL CORP·Filed 2023·Application pending·0 cites
- 1848US2024222447A1Gate cut, and source and drain contactsINTEL CORP·Filed 2022·Application pending·0 cites
- 1941US2021183761A1Line patterning in integrated circuit devicesINTEL CORP·Filed 2019·Application pending·0 cites
- 2032US10038213B2Group IV metal or semiconductor nanowire fabricKORGEL BRIAN A·Filed 2011·Granted Jul 31, 2018·0 cites·31 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →