Inventor · disambiguated record
Reno L. Sanchez
Also filed as: SANCHEZ RENO L · SANCHEZ RENO LEE
8 granted patents·1 pending application·365 citations·filing 2002–2015
90Inventor score
Top patents by PatentIndex Score
9 records- 0194US6941538B2Method and system for integrating cores in FPGA-based system-on-chip (SoC)XILINX INC·Filed 2002·Granted Sep 6, 2005·87 cites·13 claims
- 0293US7058921B1Method and system for resource allocation in FPGA-based system-on-chip (SoC)XILINX INC·Filed 2002·Granted Jun 6, 2006·96 cites·30 claims
- 0388US6754882B1Method and system for creating a customized support package for an FPGA-based system-on-chip (SoC)XILINX INC·Filed 2002·Granted Jun 22, 2004·47 cites·9 claims
- 0487US6760898B1Method and system for inserting probe points in FPGA-based system-on-chip (SoC)XILINX INC·Filed 2002·Granted Jul 6, 2004·54 cites·30 claims
- 0584US7552415B2Method and system for creating a customized support package for an FPGA-based system-on-chip (SoC)XILINX INC·Filed 2004·Granted Jun 23, 2009·33 cites·10 claims
- 0684US6996796B2Method and system for creating a customized support package for an FPGA-based system-on-chip (SoC)XILINX INC·Filed 2004·Granted Feb 7, 2006·33 cites·20 claims
- 0781US7216328B2Method and system for integrating cores in FPGA-based system-on-chip (SoC)XILINX INC·Filed 2005·Granted May 8, 2007·9 cites·9 claims
- 0876US7509614B2Method and system for integrating cores in FPGA-based system-on-chip (SoC)XILINX INC·Filed 2005·Granted Mar 24, 2009·6 cites·12 claims
- 0930US2015319390A1Stacked and tiled focal plane arraySANDIA CORP·Filed 2015·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →