Inventor · disambiguated record
Richard A. Carberry
Also filed as: CARBERRY RICHARD A · CARBERRY RICHARD ALADINE
30 granted patents·3,547 citations·filing 1976–2004
98Inventor score
Top patents by PatentIndex Score
30 records- 0199US6529040B1FPGA lookup table with speed read decoderXILINX INC·Filed 2000·Granted Mar 4, 2003·241 cites·21 claims
- 0299US6480954B2Method of time multiplexing a programmable logic deviceXILINX INC·Filed 2001·Granted Nov 12, 2002·318 cites·13 claims
- 0399US6292019B1Programmable logic device having configurable logic blocks with user-accessible input multiplexersXILINX INC·Filed 2000·Granted Sep 18, 2001·192 cites·15 claims
- 0499US6150838AFPGA configurable logic block with multi-purpose logic/memory circuitXILINX INC·Filed 1999·Granted Nov 21, 2000·315 cites·37 claims
- 0599US5629637AMethod of time multiplexing a programmable logic deviceXILINX INC·Filed 1995·Granted May 13, 1997·295 cites·14 claims
- 0699US5600263AConfiguration modes for a time multiplexed programmable logic deviceXILINX INC·Filed 1995·Granted Feb 4, 1997·285 cites·13 claims
- 0798US5978260AMethod of time multiplexing a programmable logic deviceXILINX INC·Filed 1998·Granted Nov 2, 1999·164 cites·56 claims
- 0898US5778439AProgrammable logic device with hierarchical confiquration and state storageXILINX INC·Filed 1995·Granted Jul 7, 1998·226 cites·20 claims
- 0998US5646545ATime multiplexed programmable logic deviceXILINX INC·Filed 1995·Granted Jul 8, 1997·475 cites·65 claims
- 1097US5583450ASequencer for a time multiplexed programmable logic deviceXILINX INC·Filed 1995·Granted Dec 10, 1996·182 cites·27 claims
- 1196US6263430B1Method of time multiplexing a programmable logic deviceXILINX INC·Filed 1999·Granted Jul 17, 2001·96 cites·8 claims
- 1295US6525565B2Double data rate flip-flopXILINX INC·Filed 2001·Granted Feb 25, 2003·43 cites·11 claims
- 1395US6208163B1FPGA configurable logic block with multi-purpose logic/memory circuitXILINX INC·Filed 1999·Granted Mar 27, 2001·87 cites·11 claims
- 1494US6501296B2Logic/memory circuit having a plurality of operating modesXILINX INC·Filed 2001·Granted Dec 31, 2002·47 cites·24 claims
- 1592US6777980B2Double data rate flip-flopXILINX INC·Filed 2003·Granted Aug 17, 2004·29 cites·8 claims
- 1692US6621296B2FPGA lookup table with high speed read decorderXILINX INC·Filed 2002·Granted Sep 16, 2003·37 cites·11 claims
- 1789US4394736AData processing system utilizing a unique two-level microcoding technique for forming microinstructionsDATA GENERAL CORP·Filed 1980·Granted Jul 19, 1983·41 cites·10 claims
- 1888US6184712B1FPGA configurable logic block with multi-purpose logic/memory circuitXILINX INC·Filed 1999·Granted Feb 6, 2001·60 cites·10 claims
- 1988US5959881AProgrammable logic device including configuration data or user data memory slicesXILINX INC·Filed 1997·Granted Sep 28, 1999·100 cites·7 claims
- 2086US6373279B1FPGA lookup table with dual ended writes for ram and shift register modesXILINX INC·Filed 2000·Granted Apr 16, 2002·31 cites·8 claims
- 2183US4794524APipelined single chip microprocessor having on-chip cache and on-chip memory management unitZILOG INC·Filed 1984·Granted Dec 27, 1988·62 cites·10 claims
- 2283US4371925AData processing system having unique bus control operationDATA GENERAL CORP·Filed 1980·Granted Feb 1, 1983·29 cites·17 claims
- 2382US5784313AProgrammable logic device including configuration data or user data memory slicesXILINX INC·Filed 1995·Granted Jul 21, 1998·68 cites·9 claims
- 2479US7317773B2Double data rate flip-flopXILINX INC·Filed 2004·Granted Jan 8, 2008·11 cites·16 claims
- 2574US6288569B1Memory array with hard and soft decodersXILINX INC·Filed 2000·Granted Sep 11, 2001·12 cites·14 claims
- 2671US6445209B1FPGA lookup table with NOR gate write decoder and high speed read decoderXILINX INC·Filed 2000·Granted Sep 3, 2002·14 cites·15 claims
- 2768US5578946AInput synchronization mechanism for inside/outside clockXILINX INC·Filed 1995·Granted Nov 26, 1996·52 cites·21 claims
- 2865US5933369ARAM with synchronous write port using dynamic latchesXILINX INC·Filed 1997·Granted Aug 3, 1999·21 cites·18 claims
- 2953US6078528ADelay control circuit using dynamic latchesXILINX INC·Filed 1999·Granted Jun 20, 2000·12 cites·15 claims
- 3038US4016551ADynamic MOS memory with reduced propagation delayDATA GENERAL CORP·Filed 1976·Granted Apr 5, 1977·2 cites·5 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →