Inventor · disambiguated record
Richard K. Eguchi
Also filed as: EGUCHI RICHARD · EGUCHI RICHARD K · EGUCHI RICHARD KAZUKI
34 granted patents·1 pending application·320 citations·filing 1999–2020
97Inventor score
Top patents by PatentIndex Score
35 records- 0194US7649782B2Non-volatile memory having a dynamically adjustable soft program verify voltage level and method thereforFREESCALE SEMICONDUCTOR INC·Filed 2007·Granted Jan 19, 2010·33 cites·20 claims
- 0291US7865797B2Memory device with adjustable read reference based on ECC and method thereofFREESCALE SEMICONDUCTOR INC·Filed 2006·Granted Jan 4, 2011·26 cites·20 claims
- 0389US6226200B1In-circuit memory array bit cell threshold voltage distribution measurementMOTOROLA INC·Filed 1999·Granted May 1, 2001·84 cites·24 claims
- 0488US8504884B2Threshold voltage techniques for detecting an imminent read failure in a memory arrayEGUCHI RICHARD K·Filed 2009·Granted Aug 6, 2013·23 cites·21 claims
- 0586US9508397B1Non-volatile memory (NVM) with endurance controlFREESCALE SEMICONDUCTOR INC·Filed 2015·Granted Nov 29, 2016·8 cites·19 claims
- 0686US8687428B2Built-in self trim for non-volatile memory reference currentHE CHEN·Filed 2011·Granted Apr 1, 2014·9 cites·8 claims
- 0783US6937047B2Integrated circuit with test pad structure and method of testingFREESCALE SEMICONDUCTOR INC·Filed 2003·Granted Aug 30, 2005·36 cites·38 claims
- 0881US8095836B2Time-based techniques for detecting an imminent read failure in a memory arrayEGUCHI RICHARD K·Filed 2009·Granted Jan 10, 2012·13 cites·20 claims
- 0979US10573364B1Magnetic disturb diagnostic system for MRAMNXP USA INC·Filed 2018·Granted Feb 25, 2020·4 cites·20 claims
- 1078US9224478B2Temperature-based adaptive erase or program parallelismEGUCHI RICHARD K·Filed 2013·Granted Dec 29, 2015·6 cites·18 claims
- 1174US8902667B2Methods and systems for adjusting NVM cell bias conditions for program/erase operations to reduce performance degradationMU FUCHEN·Filed 2012·Granted Dec 2, 2014·5 cites·20 claims
- 1274US8572445B2Non-volatile memory (NVM) with imminent error predictionEGUCHI RICHARD K·Filed 2010·Granted Oct 29, 2013·4 cites·14 claims
- 1374US8516213B2Method and apparatus for EEPROM emulation for preventing data loss in the event of a flash block failureHE CHEN·Filed 2010·Granted Aug 20, 2013·5 cites·23 claims
- 1474US7545679B1Electrical erasable programmable memory transconductance testingFREESCALE SEMICONDUCTOR INC·Filed 2007·Granted Jun 9, 2009·9 cites·20 claims
- 1571US9082510B2Non-volatile memory (NVM) with adaptive write operationsHE CHEN·Filed 2012·Granted Jul 14, 2015·4 cites·12 claims
- 1671US8509001B2Adaptive write procedures for non-volatile memoryHE CHEN·Filed 2011·Granted Aug 13, 2013·4 cites·20 claims
- 1768US6826103B2Auto-tuneable reference circuit for flash EEPROM productsFREESCALE SEMICONDUCTOR INC·Filed 2002·Granted Nov 30, 2004·17 cites·15 claims
- 1866US9318163B2Robust memory start-up using clock counterEGUCHI RICHARD K·Filed 2013·Granted Apr 19, 2016·3 cites·20 claims
- 1966US7782664B2Method for electrically trimming an NVM reference cellFREESCALE SEMICONDUCTOR INC·Filed 2008·Granted Aug 24, 2010·6 cites·18 claims
- 2065US9329921B2Imminent read failure detection using high/low read voltage levelsWEILEMANN II JON W·Filed 2014·Granted May 3, 2016·2 cites·20 claims
- 2163US8289773B2Non-volatile memory (NVM) erase operation with brownout recovery techniqueEGUCHI RICHARD K·Filed 2010·Granted Oct 16, 2012·3 cites·20 claims
- 2262US9318161B2Non-volatile memory robust start-up using analog-to-digital converterEGUCHI RICHARD K·Filed 2012·Granted Apr 19, 2016·2 cites·20 claims
- 2361US10109356B2Method and apparatus for stressing a non-volatile memoryFREESCALE SEMICONDUCTOR INC·Filed 2015·Granted Oct 23, 2018·2 cites·20 claims
- 2461US8427877B2Digital method to obtain the I-V curves of NVM bitcellsHE CHEN·Filed 2011·Granted Apr 23, 2013·2 cites·22 claims
- 2560US9329932B2Imminent read failure detection based upon unacceptable wear for NVM cellsWEILEMANN II JON W·Filed 2014·Granted May 3, 2016·1 cites·20 claims
- 2660US8432752B2Adaptive write procedures for non-volatile memory using verify readEGUCHI RICHARD K·Filed 2011·Granted Apr 30, 2013·2 cites·20 claims
- 2760US7640389B2Non-volatile memory having a multiple block erase mode and method thereforFREESCALE SEMICONDUCTOR INC·Filed 2006·Granted Dec 29, 2009·1 cites·20 claims
- 2858US8782478B2Non-volatile memory (NVM) with imminent error predictionEGUCHI RICHARD K·Filed 2013·Granted Jul 15, 2014·1 cites·18 claims
- 2953US8977914B2Stress-based techniques for detecting an imminent read failure in a non-volatile memory arrayEGUCHI RICHARD K·Filed 2012·Granted Mar 10, 2015·1 cites·18 claims
- 3050US9329933B2Imminent read failure detection based upon changes in error voltage windows for NVM cellsWEILEMANN II JON W·Filed 2014·Granted May 3, 2016·1 cites·20 claims
- 3150US7599236B2In-circuit Vt distribution bit counter for non-volatile memory devicesFREESCALE SEMICONDUCTOR INC·Filed 2006·Granted Oct 6, 2009·3 cites·8 claims
- 3245US11056160B2Non-volatile memory with selectable hard writeNXP USA INC·Filed 2019·Granted Jul 6, 2021·0 cites·20 claims
- 3345US9076508B2Built-in self trim for non-volatile memory reference currentHE CHEN·Filed 2014·Granted Jul 7, 2015·0 cites·9 claims
- 3443US11581030B2Resistive memory with adjustable write parameterNXP USA INC·Filed 2020·Granted Feb 14, 2023·0 cites·22 claims
- 3529US2004123181A1Self-repair of memory arrays using preallocated redundancy (PAR) architectureFiled 2002·Application pending·0 cites
Join the waitlist — get patent alerts
Get an alert when Richard K. Eguchi files or is granted a new patent.
We store only your email — no account needed. See our privacy policy.
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →