Inventor · disambiguated record
Richard Nicholas Iachetta, Jr.
Also filed as: IACHETTA JR RICHARD NICHOLAS · IACHETTA RICHARD NICHOLAS
13 granted patents·337 citations·filing 1995–2003
93Inventor score
Files withIBM13
Top patents by PatentIndex Score
13 records- 0174US7080269B2Method and apparatus for implementing power-saving sleep mode in design with multiple clock domainsIBM·Filed 2003·Granted Jul 18, 2006·20 cites·30 claims
- 0271US6081874ANon-uniform memory access (NUMA) data processing system that speculatively issues requests on a node interconnectIBM·Filed 1998·Granted Jun 27, 2000·58 cites·18 claims
- 0368US6067611ANon-uniform memory access (NUMA) data processing system that buffers potential third node transactions to decrease communication latencyIBM·Filed 1998·Granted May 23, 2000·52 cites·14 claims
- 0465US5727171AMethod and apparatus for allowing multi-speed synchronous communications between a processor and both slow and fast computing devicesIBM·Filed 1995·Granted Mar 10, 1998·49 cites·17 claims
- 0563US6829677B1Method and apparatus for preserving the contents of synchronous DRAM through system resetIBM·Filed 2000·Granted Dec 7, 2004·18 cites·13 claims
- 0662US6973520B2System and method for providing improved bus utilization via target directed completionIBM·Filed 2002·Granted Dec 6, 2005·8 cites·23 claims
- 0759US6192452B1Method and system for avoiding data loss due to cancelled transactions within a non-uniform memory access systemIBM·Filed 1999·Granted Feb 20, 2001·37 cites·8 claims
- 0858US5864664AApparatus and method for protecting system serial number while allowing motherboard replacementIBM·Filed 1996·Granted Jan 26, 1999·38 cites·9 claims
- 0957US6801977B2Method and apparatus for passing messages through a bus-to-bus bridge while maintaining orderingIBM·Filed 2002·Granted Oct 5, 2004·5 cites·20 claims
- 1047US6085293ANon-uniform memory access (NUMA) data processing system that decreases latency by expediting rerun requestsIBM·Filed 1998·Granted Jul 4, 2000·19 cites·3 claims
- 1142US6178472B1Queue having distributed multiplexing logicIBM·Filed 1998·Granted Jan 23, 2001·14 cites·21 claims
- 1235US5867037AMethod and apparatus of programming FPGA devices through ASIC devicesIBM·Filed 1996·Granted Feb 2, 1999·9 cites·4 claims
- 1333US6055600AMethod and apparatus for detecting the presence and identification of level two cache modulesIBM·Filed 1996·Granted Apr 25, 2000·10 cites·9 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →