Inventor · disambiguated record
Richard A. Lemay
Also filed as: CURLEY JOHN L · LEMAY RICHARD · LEMAY RICHARD A · WOODS WILLIAM E
46 granted patents·1,219 citations·filing 1975–1995
99Inventor score
Technology areasG06F
Files withHONEYWELL INF SYSTEMS25BULL HN INFORMATION SYST18HONEYWELL BULL2HUTTON PRC TECHNOLOGY PARTNERS1
Top patents by PatentIndex Score
46 records- 0194US4050097ASynchronization technique for data transfers over an asynchronous common bus network coupling data processing apparatusHONEYWELL INF SYSTEMS·Filed 1976·Granted Sep 20, 1977·97 cites·12 claims
- 0292US3997896AData processing system providing split bus cycle operationHONEYWELL INF SYSTEMS·Filed 1975·Granted Dec 14, 1976·94 cites·16 claims
- 0392US3993981AApparatus for processing data transfer requests in a data processing systemHONEYWELL INF SYSTEMS·Filed 1975·Granted Nov 23, 1976·102 cites·16 claims
- 0488US4133030AControl system providing for the transfer of data in a communications processing system employing channel dedicated control blocksHONEYWELL INF SYSTEMS·Filed 1977·Granted Jan 2, 1979·71 cites·14 claims
- 0584US4206503AMultiple length address formation in a microprogrammed data processing systemHONEYWELL INF SYSTEMS·Filed 1978·Granted Jun 3, 1980·51 cites·4 claims
- 0683US5193181ARecovery method and apparatus for a pipelined processing unit of a multiprocessor systemBULL HN INFORMATION SYST·Filed 1990·Granted Mar 9, 1993·102 cites·18 claims
- 0779US4181974ASystem providing multiple outstanding information requestsHONEYWELL INF SYSTEMS·Filed 1978·Granted Jan 1, 1980·39 cites·17 claims
- 0875US4254462AHardware/firmware communication line adapterHONEYWELL INF SYSTEMS·Filed 1978·Granted Mar 3, 1981·35 cites·4 claims
- 0969US4378591AMemory management unit for developing multiple physical addresses in parallel for use in a cache memoryHONEYWELL INF SYSTEMS·Filed 1980·Granted Mar 29, 1983·35 cites·10 claims
- 1067US5678032AMethod of optimizing the execution of program instuctions by an emulator using a plurality of execution unitsBULL HN INFORMATION SYST·Filed 1995·Granted Oct 14, 1997·60 cites·21 claims
- 1162US5983012AExecuting programs of a first system on a second systemBULL HN INFORMATION SYST·Filed 1993·Granted Nov 9, 1999·45 cites·9 claims
- 1262US4236203ASystem providing multiple fetch bus cycle operationHONEYWELL INF SYSTEMS·Filed 1978·Granted Nov 25, 1980·22 cites·19 claims
- 1359US4872110AStorage of input/output command timeout and acknowledge responsesBULL HN INFORMATION SYST·Filed 1987·Granted Oct 3, 1989·25 cites·21 claims
- 1459US4261033ACommunications processor employing line-dedicated memory tables for supervising data transfersHONEYWELL INF SYSTEMS·Filed 1977·Granted Apr 7, 1981·22 cites·11 claims
- 1557US5136500AMultiple shared memory arrangement wherein multiple processors individually and concurrently access any one of plural memoriesHONEYWELL INF SYSTEMS·Filed 1989·Granted Aug 4, 1992·24 cites·11 claims
- 1656US4809276AMemory failure detection apparatusHUTTON PRC TECHNOLOGY PARTNERS·Filed 1987·Granted Feb 28, 1989·26 cites·5 claims
- 1755US5375248AMethod for organizing state machine by selectively grouping status signals as inputs and classifying commands to be executed into performance sensitive and nonsensitive categoriesBULL HN INFORMATION SYST·Filed 1993·Granted Dec 20, 1994·24 cites·2 claims
- 1855US5291580AHigh performance burst read data transfer operationBULL HN INFORMATION SYST·Filed 1991·Granted Mar 1, 1994·29 cites·12 claims
- 1955US5142682ATwo-level priority arbiter generating a request to the second level before first-level arbitration is completedBULL HN INFORMATION SYST·Filed 1991·Granted Aug 25, 1992·32 cites·8 claims
- 2052US5341495ABus controller having state machine for translating commands and controlling accesses from system bus to synchronous bus having different bus protocolsBULL HN INFORMATION SYST·Filed 1991·Granted Aug 23, 1994·25 cites·15 claims
- 2150US4225921ATransfer control technique between two units included in a data processing systemHONEYWELL INF SYSTEMS·Filed 1978·Granted Sep 30, 1980·14 cites·15 claims
- 2249US4903197AMemory bank selection arrangement generating first bits identifying a bank of memory and second bits addressing identified bankBULL HN INFORMATION SYST·Filed 1987·Granted Feb 20, 1990·16 cites·10 claims
- 2348US4245299ASystem providing adaptive response in information requesting unitHONEYWELL INF SYSTEMS·Filed 1978·Granted Jan 13, 1981·12 cites·13 claims
- 2447US4604685ATwo stage selection based on time of arrival and predetermined priority in a bus priority resolverHONEYWELL INF SYSTEMS·Filed 1984·Granted Aug 5, 1986·15 cites·12 claims
- 2547US4455606ALogic control system for efficient memory to CPU transfersHONEYWELL INF SYSTEMS·Filed 1981·Granted Jun 19, 1984·14 cites·4 claims
- 2646US5280595AState machine for executing commands within a minimum number of cycles by accomodating unforseen time dependency according to status signals received from different functional sectionsBULL HN INFORMATION SYST·Filed 1990·Granted Jan 18, 1994·15 cites·13 claims
- 2744US5491790APower-on sequencing apparatus for initializing and testing a system processing unitBULL HN INFORMATION SYST·Filed 1994·Granted Feb 13, 1996·16 cites·12 claims
- 2844US4451883ABus sourcing and shifter control of a central processing unitHONEYWELL INF SYSTEMS·Filed 1981·Granted May 29, 1984·13 cites·12 claims
- 2943US5293384AMicroprocessor bus interface protocol analyzerBULL HN INFORMATION SYST·Filed 1991·Granted Mar 8, 1994·14 cites·12 claims
- 3043US4837738AAddress boundary detectorHONEYWELL INF SYSTEMS·Filed 1986·Granted Jun 6, 1989·12 cites·2 claims
- 3142US5341501AProcessor bus accessBULL HN INFORMATION SYST·Filed 1991·Granted Aug 23, 1994·13 cites·11 claims
- 3242US4964037AMemory addressing arrangementBULL HN INFORMATION SYST·Filed 1987·Granted Oct 16, 1990·11 cites·1 claims
- 3342US4811266AMultifunction arithmetic indicatorHONEYWELL BULL·Filed 1986·Granted Mar 7, 1989·11 cites·3 claims
- 3442US4308589AApparatus for performing the scientific add instructionHONEYWELL INF SYSTEMS·Filed 1979·Granted Dec 29, 1981·9 cites·14 claims
- 3540US5446847AProgrammable system bus priority networkBULL HN INFORMATION SYST·Filed 1993·Granted Aug 29, 1995·11 cites·11 claims
- 3639US5274825AMicroprocessor vectored interruptsBULL HN INFORMATION SYST·Filed 1992·Granted Dec 28, 1993·11 cites·3 claims
- 3739US4460959ALogic control system including cache memory for CPU-memory transfersHONEYWELL INF SYSTEMS·Filed 1981·Granted Jul 17, 1984·9 cites·3 claims
- 3837US4935737AData selection matrixBULL HN INFORMATION SYST·Filed 1986·Granted Jun 19, 1990·8 cites·4 claims
- 3936US4472773AInstruction decoding logic systemHONEYWELL INF SYSTEMS·Filed 1981·Granted Sep 18, 1984·7 cites·4 claims
- 4035US4727486AHardware demand fetch cycle system interfaceHONEYWELL INF SYSTEMS·Filed 1986·Granted Feb 23, 1988·7 cites·12 claims
- 4135US4305134AAutomatic operand length control of the result of a scientific arithmetic operationHONEYWELL INF SYSTEMS·Filed 1979·Granted Dec 8, 1981·5 cites·6 claims
- 4233US5161217ABuffered address stack register with parallel input registers and overflow protectionBULL HN INFORMATION SYST·Filed 1989·Granted Nov 3, 1992·5 cites·4 claims
- 4333US4349874ABuffer system for supply procedure words to a central processor unitHONEYWELL INF SYSTEMS·Filed 1980·Granted Sep 14, 1982·5 cites·11 claims
- 4431US4467416ALogic transfer and decoding systemHONEYWELL INF SYSTEMS·Filed 1981·Granted Aug 21, 1984·3 cites·4 claims
- 4530US4467417AFlexible logic transfer and instruction decoding systemHONEYWELL INF SYSTEMS·Filed 1981·Granted Aug 21, 1984·2 cites·3 claims
- 4625US4775929ATime partitioned bus arrangementHONEYWELL BULL·Filed 1986·Granted Oct 4, 1988·1 cites·7 claims
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