Inventor · disambiguated record
Richard E. Perego
Also filed as: PEREGO RICHARD · PEREGO RICHARD E
145 granted patents·18 pending applications·4,405 citations·filing 1997–2025
99Inventor score
Files withRAMBUS INC126PEREGO RICHARD E10WARE FREDERICK A10ADEIA SEMICONDUCTOR TECH LLC3HAMPEL CRAIG E3
Top patents by PatentIndex Score
163 records- 0199US7043599B1Dynamic memory supporting simultaneous refresh and data-access transactionsRAMBUS INC·Filed 2002·Granted May 9, 2006·246 cites·95 claims
- 0299US7003618B2System featuring memory modules that include an integrated circuit buffer devicesRAMBUS INC·Filed 2005·Granted Feb 21, 2006·103 cites·24 claims
- 0399US7000062B2System and method featuring a controller device and a memory module that includes an integrated circuit buffer device and a plurality of integrated circuit memory devicesRAMBUS INC·Filed 2005·Granted Feb 14, 2006·185 cites·28 claims
- 0499US6889304B2Memory device supporting a dynamically configurable core organizationRAMBUS INC·Filed 2002·Granted May 3, 2005·314 cites·14 claims
- 0599US6675272B2Method and apparatus for coordinating memory operations among diversely-located memory componentsRAMBUS INC·Filed 2001·Granted Jan 6, 2004·224 cites·28 claims
- 0699US6502161B1Memory system including a point-to-point linked memory subsystemRAMBUS INC·Filed 2000·Granted Dec 31, 2002·596 cites·49 claims
- 0798US11727966B2Memory controllers, systems, and methods supporting multiple request modesRAMBUS INC·Filed 2022·Granted Aug 15, 2023·3 cites·20 claims
- 0898US11276440B2Memory controllers, systems, and methods supporting multiple request modesRAMBUS INC·Filed 2020·Granted Mar 15, 2022·6 cites·20 claims
- 0998US8359445B2Method and apparatus for signaling between devices of a memory systemRAMBUS INC·Filed 2009·Granted Jan 22, 2013·62 cites·35 claims
- 1098US7210016B2Method, system and memory controller utilizing adjustable write data delay settingsRAMBUS INC·Filed 2005·Granted Apr 24, 2007·47 cites·24 claims
- 1198US7209397B2Memory device with clock multiplier circuitRAMBUS INC·Filed 2005·Granted Apr 24, 2007·56 cites·22 claims
- 1298US7177998B2Method, system and memory controller utilizing adjustable read data delay settingsRAMBUS INC·Filed 2006·Granted Feb 13, 2007·50 cites·24 claims
- 1398US7010642B2System featuring a controller device and a memory module that includes an integrated circuit buffer device and a plurality of integrated circuit memory devicesRAMBUS INC·Filed 2004·Granted Mar 7, 2006·119 cites·44 claims
- 1498US6920540B2Timing calibration apparatus and method for a memory device signaling systemRAMBUS INC·Filed 2002·Granted Jul 19, 2005·128 cites·67 claims
- 1597US8717837B2Memory moduleRAMBUS INC·Filed 2013·Granted May 6, 2014·20 cites·20 claims
- 1697US8625371B2Memory component with terminated and unterminated signaling inputsRAMBUS INC·Filed 2013·Granted Jan 7, 2014·20 cites·20 claims
- 1797US8537601B2Memory controller with selective data transmission delayWARE FREDERICK A·Filed 2012·Granted Sep 17, 2013·20 cites·18 claims
- 1897US8144792B2Communication channel calibration for drift conditionsWARE FREDERICK A·Filed 2007·Granted Mar 27, 2012·42 cites·34 claims
- 1997US8069379B2Memory system with point-to-point request interconnectPEREGO RICHARD E·Filed 2009·Granted Nov 29, 2011·42 cites·16 claims
- 2097US7577789B2Upgradable memory system with reconfigurable interconnectRAMBUS INC·Filed 2006·Granted Aug 18, 2009·50 cites·28 claims
- 2197US7400671B2Periodic calibration for communication channels by drift trackingRAMBUS INC·Filed 2007·Granted Jul 15, 2008·34 cites·19 claims
- 2297US7225292B2Memory module with termination componentRAMBUS INC·Filed 2005·Granted May 29, 2007·42 cites·22 claims
- 2397US7200055B2Memory module with termination componentRAMBUS INC·Filed 2005·Granted Apr 3, 2007·42 cites·24 claims
- 2496US10236051B2Memory controllerRAMBUS INC·Filed 2017·Granted Mar 19, 2019·7 cites·20 claims
- 2596US8462566B2Memory module with termination componentWARE FREDERICK A·Filed 2008·Granted Jun 11, 2013·24 cites·34 claims
- 2696US7565480B2Dynamic memory supporting simultaneous refresh and data-access transactionsRAMBUS INC·Filed 2005·Granted Jul 21, 2009·46 cites·25 claims
- 2796US6765800B2Multiple channel modules and bus systems using sameRAMBUS INC·Filed 2001·Granted Jul 20, 2004·73 cites·14 claims
- 2895US9472262B2Memory controllerRAMBUS INC·Filed 2016·Granted Oct 18, 2016·6 cites·20 claims
- 2995US9311976B2Memory moduleRAMBUS INC·Filed 2014·Granted Apr 12, 2016·11 cites·20 claims
- 3095US9053778B2Memory controller that enforces strobe-to-strobe timing offsetRAMBUS INC·Filed 2013·Granted Jun 9, 2015·13 cites·20 claims
- 3195US8924680B2Memory controllers, systems, and methods supporting multiple request modesPEREGO RICHARD E·Filed 2008·Granted Dec 30, 2014·29 cites·47 claims
- 3295US8261039B2Memory controllers, methods, and systems supporting multiple memory modesPEREGO RICHARD E·Filed 2010·Granted Sep 4, 2012·19 cites·28 claims
- 3395US8214616B2Memory controller device having timing offset capabilityWARE FREDERICK A·Filed 2007·Granted Jul 3, 2012·22 cites·55 claims
- 3495US7484064B2Method and apparatus for signaling between devices of a memory systemRAMBUS INC·Filed 2001·Granted Jan 27, 2009·54 cites·36 claims
- 3595US7363422B2Configurable width buffered moduleRAMBUS INC·Filed 2004·Granted Apr 22, 2008·128 cites·41 claims
- 3695US7320047B2System having a controller device, a buffer device and a plurality of memory devicesRAMBUS INC·Filed 2005·Granted Jan 15, 2008·30 cites·32 claims
- 3795US7225311B2Method and apparatus for coordinating memory operations among diversely-located memory componentsRAMBUS INC·Filed 2003·Granted May 29, 2007·52 cites·78 claims
- 3895US7095789B2Communication channel calibration for drift conditionsRAMBUS INC·Filed 2004·Granted Aug 22, 2006·61 cites·43 claims
- 3994US7526597B2Buffered memory having a control bus and dedicated data linesRAMBUS INC·Filed 2007·Granted Apr 28, 2009·38 cites·24 claims
- 4094US6898085B2Multiple channel modules and bus systems using sameRAMBUS INC·Filed 2003·Granted May 24, 2005·61 cites·24 claims
- 4194US6772315B1Translation lookaside buffer extended to provide physical and main-memory addressesRAMBUS INC·Filed 2001·Granted Aug 3, 2004·97 cites·28 claims
- 4294US6636935B1Techniques for increasing bandwidth in port-per-module memory systems having mismatched memory modulesRAMBUS INC·Filed 2001·Granted Oct 21, 2003·93 cites·17 claims
- 4393US9741424B2Memory controllerRAMBUS INC·Filed 2016·Granted Aug 22, 2017·4 cites·20 claims
- 4493US8395951B2Memory controllerWARE FREDERICK A·Filed 2012·Granted Mar 12, 2013·9 cites·38 claims
- 4593US7313639B2Memory system and device with serialized data transferRAMBUS INC·Filed 2003·Granted Dec 25, 2007·47 cites·21 claims
- 4692US10706910B2Memory controllerRAMBUS INC·Filed 2019·Granted Jul 7, 2020·4 cites·20 claims
- 4792US10192609B2Memory component with pattern register circuitry to provide data patterns for calibrationRAMBUS INC·Filed 2017·Granted Jan 29, 2019·6 cites·20 claims
- 4892US8391039B2Memory module with termination componentWARE FREDERICK A·Filed 2005·Granted Mar 5, 2013·25 cites·11 claims
- 4992US7965567B2Phase adjustment apparatus and method for a memory device signaling systemRAMBUS INC·Filed 2007·Granted Jun 21, 2011·14 cites·25 claims
- 5092US7668276B2Phase adjustment apparatus and method for a memory device signaling systemRAMBUS INC·Filed 2002·Granted Feb 23, 2010·37 cites·26 claims
Showing the top 50 of 163 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →