Inventor · disambiguated record
Richard S. Rodgers
Also filed as: RODGERS RICHARD · RODGERS RICHARD S
11 granted patents·2 pending applications·56 citations·filing 2002–2012
87Inventor score
Files withAVAGO TECHNOLOGIES GENERAL IP4AGILENT TECHNOLOGIES INC2RODGERS RICHARD2AVAGO TECHNOLOGIES ENTPR IP SI1ESCH GERALD L JR1
Top patents by PatentIndex Score
13 records- 0181US8332802B2Systems, methods, and programs for leakage power and timing optimization in integrated circuit designsHAUGESTUEN BENJAMIN P·Filed 2010·Granted Dec 11, 2012·13 cites·17 claims
- 0278US7386824B2Determining the placement of semiconductor components on an integrated circuitAVAGO TECHNOLOGIES GENERAL IP·Filed 2005·Granted Jun 10, 2008·8 cites·18 claims
- 0373US6769104B2Method and apparatus for minimizing clock skew in a balanced tree when interfacing to an unbalanced loadAGILENT TECHNOLOGIES INC·Filed 2002·Granted Jul 27, 2004·21 cites·10 claims
- 0467US7451418B2Alpha-particle-tolerant semiconductor die systems, devices, components and methods for optimizing clock rates and minimizing die sizeAVAGO TECHNOLOGIES ENTPR IP SI·Filed 2006·Granted Nov 11, 2008·4 cites·35 claims
- 0562US8472311B2Systems, methods, and computer readable media for providing instantaneous failover of packet processing elements in a networkRODGERS RICHARD·Filed 2010·Granted Jun 25, 2013·4 cites·30 claims
- 0654US7079973B2Apparatus and method for compensating clock period elongation during scan testing in an integrated circuit (IC)AVAGO TECHNOLOGIES GENERAL IP·Filed 2004·Granted Jul 18, 2006·6 cites·10 claims
- 0751US7915742B2Determining the placement of semiconductor components on an integrated circuitAVAGO TECHNOLOGIES GENERAL IP·Filed 2008·Granted Mar 29, 2011·0 cites·10 claims
- 0844US2005262464A1Integrated circuit routing resource optimization algorithm for random port orderingESCH GERALD L JR·Filed 2005·Application pending·0 cites
- 0943US7010641B2Integrated circuit routing resource optimization algorithm for random port orderingAGILENT TECHNOLOGIES INC·Filed 2003·Granted Mar 7, 2006·0 cites·9 claims
- 1041US7580806B2Apparatus and method for compensating clock period elongation during scan testing in an integrated circuit (IC)AVAGO TECHNOLOGIES GENERAL IP·Filed 2006·Granted Aug 25, 2009·0 cites·8 claims
- 1136US2010268935A1Methods, systems, and computer readable media for maintaining flow affinity to internet protocol security (ipsec) sessions in a load-sharing security gatewayRODGERS RICHARD·Filed 2009·Application pending·0 cites
- 1233US8671376B2Computer system and method for performing a routing supply and demand analysis during the floor planning stage of an integrated circuit design processGENTRY JASON T·Filed 2012·Granted Mar 11, 2014·0 cites·31 claims
- 1333US8434052B1System and method for ensuring partitioned block physical compatibility between revisions of an integrated circuit designKOENIG BRADY A·Filed 2012·Granted Apr 30, 2013·0 cites·18 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →