Inventor · disambiguated record
Richard T. Schultz
Also filed as: SCHULTZ RICHARD · SCHULTZ RICHARD T · SCHULTZ RICHARD THOMAS
78 granted patents·14 pending applications·878 citations·filing 1996–2023
99Inventor score
Top patents by PatentIndex Score
92 records- 0197US9704995B1Gate all around device architecture with local oxideADVANCED MICRO DEVICES INC·Filed 2016·Granted Jul 11, 2017·20 cites·20 claims
- 0296US7960287B2Methods for fabricating FinFET structures having different channel lengthsGLOBALFOUNDRIES INC·Filed 2010·Granted Jun 14, 2011·25 cites·9 claims
- 0395US11881393B2Cross field effect transistor library cell architecture designADVANCED MICRO DEVICES INC·Filed 2021·Granted Jan 23, 2024·2 cites·7 claims
- 0495US7687339B1Methods for fabricating FinFET structures having different channel lengthsADVANCED MICRO DEVICES INC·Filed 2009·Granted Mar 30, 2010·38 cites·18 claims
- 0594US10438937B1Metal zero contact via redundancy on output nodes and inset power rail architectureADVANCED MICRO DEVICES INC·Filed 2018·Granted Oct 8, 2019·9 cites·13 claims
- 0694US8716124B2Trench silicide and gate open with local interconnect with replacement gate processSCHULTZ RICHARD T·Filed 2011·Granted May 6, 2014·18 cites·15 claims
- 0793US10186510B2Vertical gate all around library architectureADVANCED MICRO DEVICES INC·Filed 2017·Granted Jan 22, 2019·11 cites·17 claims
- 0893US8099686B2CAD flow for 15nm/22nm multiple fine grained wimpy gate lengths in SIT gate flowSCHULTZ RICHARD·Filed 2009·Granted Jan 17, 2012·27 cites·11 claims
- 0992US10796061B1Standard cell and power grid architectures with EUV lithographyADVANCED MICRO DEVICES INC·Filed 2019·Granted Oct 6, 2020·8 cites·20 claims
- 1092US8564030B2Self-aligned trench contact and local interconnect with replacement gate processSCHULTZ RICHARD T·Filed 2011·Granted Oct 22, 2013·17 cites·15 claims
- 1191US9006834B2Trench silicide and gate open with local interconnect with replacement gate processADVANCED MICRO DEVICES INC·Filed 2014·Granted Apr 14, 2015·11 cites·16 claims
- 1290US11652050B2Inset power post and strap architecture with reduced voltage droopADVANCED MICRO DEVICES INC·Filed 2020·Granted May 16, 2023·2 cites·16 claims
- 1390US10304728B2Double spacer immersion lithography triple patterning flow and methodADVANCED MICRO DEVICES INC·Filed 2017·Granted May 28, 2019·5 cites·12 claims
- 1489US8624320B2Process for forming fins for a FinFET deviceSCHULTZ RICHARD T·Filed 2010·Granted Jan 7, 2014·12 cites·6 claims
- 1589US8076236B2SRAM bit cell with self-aligned bidirectional local interconnectsSCHULTZ RICHARD T·Filed 2009·Granted Dec 13, 2011·16 cites·10 claims
- 1688US7829466B2Methods for fabricating FinFET structures having different channel lengthsGLOBALFOUNDRIES INC·Filed 2009·Granted Nov 9, 2010·13 cites·9 claims
- 1786US10068794B2Gate all around device architecture with hybrid wafer bond techniqueADVANCED MICRO DEVICES INC·Filed 2017·Granted Sep 4, 2018·4 cites·16 claims
- 1884US11742289B2Semiconductor chip with stacked conductor lines and air gapsADVANCED MICRO DEVICES INC·Filed 2021·Granted Aug 29, 2023·1 cites·20 claims
- 1984US11120190B2Metal zero power ground stub route to reduce cell area and improve cell placement at the chip levelADVANCED MICRO DEVICES INC·Filed 2017·Granted Sep 14, 2021·3 cites·20 claims
- 2084US10608076B2Oscillating capacitor architecture in polysilicon for improved capacitanceADVANCED MICRO DEVICES INC·Filed 2017·Granted Mar 31, 2020·4 cites·20 claims
- 2184US7154734B2Fully shielded capacitor cell structureLSI LOGIC CORP·Filed 2004·Granted Dec 26, 2006·45 cites·15 claims
- 2283US8563425B2Selective local interconnect to gate in a self aligned local interconnect processSCHULTZ RICHARD T·Filed 2009·Granted Oct 22, 2013·11 cites·20 claims
- 2383US7392496B1Device for avoiding timing violations resulting from process defects in a backfilled metal layer of an integrated circuitLSI CORP·Filed 2006·Granted Jun 24, 2008·15 cites·18 claims
- 2482US6433598B1Process, voltage and temperature independent clock tree deskew circuitry-active drive methodLSI LOGIC CORP·Filed 2001·Granted Aug 13, 2002·26 cites·24 claims
- 2581US2024321702A1Backside powerADVANCED MICRO DEVICES INC·Filed 2023·Application pending·0 cites
- 2680US10756164B2Sinusoidal shaped capacitor architecture in oxideADVANCED MICRO DEVICES INC·Filed 2017·Granted Aug 25, 2020·2 cites·7 claims
- 2780US8219939B2Method of creating photolithographic masks for semiconductor device features with reduced design rule violationsSCHULTZ RICHARD·Filed 2009·Granted Jul 10, 2012·9 cites·15 claims
- 2880US7420229B2Failure analysis vehicle for yield enhancement with self test at speed burnin capability for reliability testingLSI CORP·Filed 2006·Granted Sep 2, 2008·9 cites·9 claims
- 2980US6429714B1Process, voltage and temperature independent clock tree deskew circuitry-temporary driver methodLSI LOGIC CORP·Filed 2002·Granted Aug 6, 2002·23 cites·26 claims
- 3080US6340905B1Dynamically minimizing clock tree skew in an integrated circuitLSI LOGIC CORP·Filed 2000·Granted Jan 22, 2002·30 cites·32 claims
- 3180US2024321827A1Thermally aware stacking topologyADVANCED MICRO DEVICES INC·Filed 2023·Application pending·0 cites
- 3280US2024321668A1Temperature sensors in die pair topologyADVANCED MICRO DEVICES INC·Filed 2023·Application pending·0 cites
- 3379US11004791B2Semiconductor chip with stacked conductor lines and air gapsADVANCED MICRO DEVICES INC·Filed 2019·Granted May 11, 2021·2 cites·22 claims
- 3478US12274046B2Cross FET SRAM cell layoutADVANCED MICRO DEVICES INC·Filed 2023·Granted Apr 8, 2025·0 cites·20 claims
- 3578US10818762B2Gate contact over active region in cellADVANCED MICRO DEVICES INC·Filed 2018·Granted Oct 27, 2020·2 cites·20 claims
- 3677US7181713B2Static timing and risk analysis toolLSI LOGIC CORP·Filed 2005·Granted Feb 20, 2007·8 cites·15 claims
- 3777US6442741B1Method of automatically generating schematic and waveform diagrams for analysis of timing margins and signal skews of relevant logic cells using input signal predictors and transition timesLSI LOGIC CORP·Filed 2000·Granted Aug 27, 2002·26 cites·22 claims
- 3876US7023252B2Chip level clock tree deskew circuitLSI LOGIC CORP·Filed 2004·Granted Apr 4, 2006·23 cites·19 claims
- 3976US6675139B1Floor plan-based power bus analysis and design tool for integrated circuitsLSI LOGIC CORP·Filed 1999·Granted Jan 6, 2004·80 cites·21 claims
- 4075US7016794B2Floor plan development electromigration and voltage drop analysis toolLSI LOGIC CORP·Filed 1999·Granted Mar 21, 2006·69 cites·41 claims
- 4174US7829973B2N cell height decoupling circuitLSI CORP·Filed 2007·Granted Nov 9, 2010·9 cites·20 claims
- 4272US2024258322A1Cross field effect transistor library cell architecture designADVANCED MICRO DEVICES INC·Filed 2023·Application pending·0 cites
- 4369US11778803B2Cross FET SRAM cell layoutADVANCED MICRO DEVICES INC·Filed 2021·Granted Oct 3, 2023·0 cites·20 claims
- 4469US8347123B2Turning off clock to flip flopsLSI CORP·Filed 2009·Granted Jan 1, 2013·4 cites·10 claims
- 4569US8304172B2Semiconductor device fabrication using a multiple exposure and block mask approach to reduce design rule violationsSCHULTZ RICHARD·Filed 2009·Granted Nov 6, 2012·3 cites·18 claims
- 4669US6781151B2Failure analysis vehicleLSI LOGIC CORP·Filed 2002·Granted Aug 24, 2004·15 cites·21 claims
- 4768US12455999B2Metal zero power ground stub route to reduce cell area and improve cell placement at the chip levelADVANCED MICRO DEVICES INC·Filed 2021·Granted Oct 28, 2025·0 cites·14 claims
- 4868US6653883B2Process, voltage and temperature independent clock tree deskew circuitry-temporary driver methodLSI LOGIC CORP·Filed 2002·Granted Nov 25, 2003·10 cites·31 claims
- 4967US6851098B2Static timing analysis and performance diagnostic display toolLSI LOGIC CORP·Filed 2002·Granted Feb 1, 2005·13 cites·7 claims
- 5066US11424336B2Gate contact over active region in cellADVANCED MICRO DEVICES INC·Filed 2020·Granted Aug 23, 2022·0 cites·20 claims
Showing the top 50 of 92 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →