Inventor · disambiguated record
Robert Bedichek
Also filed as: BEDICHEK ROBERT · BEDICHEK ROBERT C
14 granted patents·449 citations·filing 1987–2010
93Inventor score
Technology areasG06F
Top patents by PatentIndex Score
14 records- 0195US6594821B1Translation consistency checking for modified target instructions by comparing to original copyTRANSMETA CORP·Filed 2000·Granted Jul 15, 2003·106 cites·24 claims
- 0292US7404181B1Switching to original code comparison of modifiable code for translated code validity when frequency of detecting memory overwrites exceeds thresholdTRANSMETA CORP·Filed 2006·Granted Jul 22, 2008·22 cites·16 claims
- 0387US7096460B1Switching to original modifiable instruction copy comparison check to validate prior translation when translated sub-area protection exception slows down operationTRANSMETA CORP·Filed 2003·Granted Aug 22, 2006·34 cites·12 claims
- 0486US5905855AMethod and apparatus for correcting errors in computer systemsTRANSMETA CORP·Filed 1997·Granted May 18, 1999·140 cites·23 claims
- 0570US6415379B1Method and apparatus for maintaining context while executing translated instructionsTRANSMETA CORP·Filed 1999·Granted Jul 2, 2002·57 cites·12 claims
- 0670US4803622AProgrammable I/O sequencer for use in an I/O processorINTEL CORP·Filed 1987·Granted Feb 7, 1989·45 cites·3 claims
- 0767US7904891B2Checking for instruction invariance to execute previously obtained translation code by comparing instruction to a copy stored when write operation to the memory portion occurBANNING JOHN·Filed 2008·Granted Mar 8, 2011·2 cites·34 claims
- 0857US7617088B1Interpage prologue to protect virtual address mappingsBEDICHEK ROBERT·Filed 2005·Granted Nov 10, 2009·1 cites·11 claims
- 0954US8418153B2Method for integration of interpretation and translation in a microprocessorBEDICHEK ROBERT·Filed 2009·Granted Apr 9, 2013·0 cites·21 claims
- 1048US6990658B1Method for translating instructions in a speculative microprocessor featuring committing stateTRANSMETA CORP·Filed 1999·Granted Jan 24, 2006·16 cites·6 claims
- 1146US6845353B1Interpage prologue to protect virtual address mappingsTRANSMETA CORP·Filed 1999·Granted Jan 18, 2005·15 cites·14 claims
- 1245US9875103B2Translating instructions in a speculative processorTORVALDS LINUS·Filed 2010·Granted Jan 23, 2018·0 cites·19 claims
- 1344US7694113B1Method for translating instructions in a speculative microprocessorTORVALDS LINUS·Filed 2005·Granted Apr 6, 2010·0 cites·8 claims
- 1439US7761857B1Method for switching between interpretation and dynamic translation in a processor system based upon code sequence execution countsBEDICHEK ROBERT·Filed 1999·Granted Jul 20, 2010·11 cites·26 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →