Inventor · disambiguated record
Robert H. Bishop
Also filed as: BISHOP ROBERT · BISHOP ROBERT H · BISHOP ROBERT HENRY
11 granted patents·3 pending applications·96 citations·filing 1997–2022
89Inventor score
Files withINTEGRATED DEVICE TECH10ADTRAN NETWORKS SE1ADVA OPTICAL NETWORKING SE1BISHOP ROBERT HENRY1SHAMARAO PRASHANT1
Top patents by PatentIndex Score
14 records- 0193US7796629B1Packet switch with configurable bandwidth allocation precisionINTEGRATED DEVICE TECH·Filed 2008·Granted Sep 14, 2010·27 cites·24 claims
- 0287US7974278B1Packet switch with configurable virtual channelsINTEGRATED DEVICE TECH·Filed 2008·Granted Jul 5, 2011·13 cites·25 claims
- 0384US8081646B1Old virtual queues technique for routing data packets in a packet switchBISHOP ROBERT HENRY·Filed 2008·Granted Dec 20, 2011·14 cites·12 claims
- 0461US9407574B2Using SerDes loopbacks for low latency functional modes with full monitoring capabilityADVA OPTICAL NETWORKING SE·Filed 2014·Granted Aug 2, 2016·1 cites·17 claims
- 0549US12155418B2Non-intrusive deskew of trunked clients in an optical network transport systemADTRAN NETWORKS SE·Filed 2022·Granted Nov 26, 2024·0 cites·10 claims
- 0649US5848019APass gate decoder for a multiport memory dEvice that uses a single ported memory cell array structureINTEGRATED DEVICE TECH·Filed 1997·Granted Dec 8, 1998·13 cites·20 claims
- 0747US8686759B2Bi-directional channel amplifierSHAMARAO PRASHANT·Filed 2010·Granted Apr 1, 2014·1 cites·24 claims
- 0847US6930400B1Grid array microelectronic packages with increased peripheryINTEGRATED DEVICE TECH·Filed 2003·Granted Aug 16, 2005·3 cites·15 claims
- 0944US2009073873A1Multiple path switch and switching algorithmsINTEGRATED DEVICE TECH·Filed 2007·Application pending·0 cites
- 1044US2009073968A1Device with modified round robin arbitration scheme and method for transferring dataINTEGRATED DEVICE TECH·Filed 2007·Application pending·0 cites
- 1144US2009074000A1Packet based switch with destination updatingINTEGRATED DEVICE TECH·Filed 2007·Application pending·0 cites
- 1243US6373757B1Integrated circuit memory devices having control circuits therein that provide column redundancy capabilityINTEGRATED DEVICE TECH·Filed 2000·Granted Apr 16, 2002·4 cites·18 claims
- 1337US6614798B1Asynchronous FIFO increment and decrement control for interfaces that operate at differing clock frequenciesINTEGRATED DEVICE TECH·Filed 1999·Granted Sep 2, 2003·13 cites·5 claims
- 1433US6266748B1Priority encoding for FIFO memory devices that interface multiple ports to a data receiving deviceINTEGRATED DEVICE TECH·Filed 1999·Granted Jul 24, 2001·7 cites·20 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →