Inventor · disambiguated record
Rolando H. Bruce
Also filed as: BRUCE ROLANDO H
16 granted patents·2 pending applications·1,889 citations·filing 1997–2019
95Inventor score
Top patents by PatentIndex Score
18 records- 0198US6000006AUnified re-map and cache-index table with dual write-counters for wear-leveling of non-volatile flash RAM mass storageBIT MICROSYSTEMS INC·Filed 1997·Granted Dec 7, 1999·1k cites·19 claims
- 0295US5822251AExpandable flash-memory mass-storage using shared buddy lines and intermediate flash-bus between device-specific buffers and flash-intelligent DMA controllersBIT MICROSYSTEMS INC·Filed 1997·Granted Oct 13, 1998·302 cites·24 claims
- 0394US9484103B1Electronic storage deviceBITMICRO NETWORKS INC·Filed 2015·Granted Nov 1, 2016·22 cites·19 claims
- 0494US9099187B2Reducing erase cycles in an electronic storage device that uses at least one erase-limited memory deviceBITMICRO NETWORKS INC·Filed 2013·Granted Aug 4, 2015·37 cites·24 claims
- 0594US6970890B1Method and apparatus for data recoveryBITMICRO NETWORKS INC·Filed 2001·Granted Nov 29, 2005·102 cites·31 claims
- 0694US5956743ATransparent management at host interface of flash-memory overhead-bytes using flash-specific DMA having programmable processor-interrupt of high-level operationsBIT MICROSYSTEMS INC·Filed 1997·Granted Sep 21, 1999·258 cites·20 claims
- 0793US8560804B2Reducing erase cycles in an electronic storage device that uses at least one erase-limited memory deviceBRUCE ROLANDO H·Filed 2010·Granted Oct 15, 2013·41 cites·24 claims
- 0893US6529416B2Parallel erase operations in memory systemsBITMICRO NETWORKS INC·Filed 2001·Granted Mar 4, 2003·71 cites·20 claims
- 0987US10210084B1Multi-leveled cache management in a hybrid storage systemBITMICRO LLC·Filed 2016·Granted Feb 19, 2019·6 cites·19 claims
- 1083US9372755B1Adaptive power cycle sequences for data recoveryBRUCE ROLANDO H·Filed 2011·Granted Jun 21, 2016·9 cites·17 claims
- 1181US10445239B1Write bufferingBITMICRO NETWORKS INC·Filed 2017·Granted Oct 15, 2019·3 cites·20 claims
- 1280US9430386B2Multi-leveled cache management in a hybrid storage systemBITMICRO NETWORKS INC·Filed 2014·Granted Aug 30, 2016·5 cites·19 claims
- 1377US9734067B1Write bufferingBITMICRO NETWORKS INC·Filed 2015·Granted Aug 15, 2017·3 cites·15 claims
- 1458US10540242B2Adaptive power cycle sequences for data recoveryBITMICRO LLC·Filed 2019·Granted Jan 21, 2020·0 cites·6 claims
- 1557US2020151098A1Write bufferingBITMICRO LLC·Filed 2019·Application pending·0 cites
- 1652US10180887B1Adaptive power cycle sequences for data recoveryBITMICRO LLC·Filed 2016·Granted Jan 15, 2019·0 cites·18 claims
- 1746US10082966B1Electronic storage deviceBITMICRO LLC·Filed 2016·Granted Sep 25, 2018·0 cites·25 claims
- 1844US2002141244A1Parallel erase operations in memory systemsFiled 2002·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →