Inventor · disambiguated record
Roy Carlson
Also filed as: CARLSON ROY · CARLSON ROY M · CARLSON ROY MILTON
12 granted patents·3 pending applications·135 citations·filing 1997–2016
91Inventor score
Files withHONEYWELL INT INC8INTEL CORP3BROADCOM CORP2AVAGO TECHNOLOGIES GENERAL IP1SCHMITT JONATHAN1
Top patents by PatentIndex Score
15 records- 0179US8031506B2One-time programmable memory cellBROADCOM CORP·Filed 2008·Granted Oct 4, 2011·9 cites·20 claims
- 0276US9007805B2Programmable diode array for high density OTP applicationBROADCOM CORP·Filed 2013·Granted Apr 14, 2015·4 cites·20 claims
- 0372US6396305B1Digital leakage compensation circuitINTEL CORP·Filed 2001·Granted May 28, 2002·17 cites·30 claims
- 0471US9136217B2One-time programmable memory cellSCHMITT JONATHAN·Filed 2012·Granted Sep 15, 2015·3 cites·20 claims
- 0566US7619455B2Digital single event transient hardened register using adaptive holdHONEYWELL INT INC·Filed 2007·Granted Nov 17, 2009·5 cites·19 claims
- 0664US6791362B1System level hardening of asynchronous combinational logicHONEYWELL INT INC·Filed 2003·Granted Sep 14, 2004·11 cites·40 claims
- 0762US6937053B2Single event hardening of null convention logic circuitsHONEYWELL INT INC·Filed 2003·Granted Aug 30, 2005·10 cites·26 claims
- 0858US6128769AMethod for analyzing and efficiently reducing signal cross-talk noiseINTEL CORP·Filed 1997·Granted Oct 3, 2000·37 cites·13 claims
- 0954US7215135B2Single event upset hardened circuitry without sensitivity to overshoot and/or undershoot conditionsHONEYWELL INT INC·Filed 2004·Granted May 8, 2007·7 cites·33 claims
- 1052US5983006AMethod for analyzing and efficiently eliminating timing problems induced by cross-coupling between signalsINTEL CORP·Filed 1997·Granted Nov 9, 1999·28 cites·13 claims
- 1147US7451384B2Error recovery in asynchronous combinational logic circuitsHONEYWELL INT INC·Filed 2004·Granted Nov 11, 2008·4 cites·24 claims
- 1238US2007162880A1Single event transient immune antenna diode circuitHONEYWELL INT INC·Filed 2006·Application pending·0 cites
- 1335US2008115023A1Set hardened registerHONEYWELL INT INC·Filed 2006·Application pending·0 cites
- 1432US2006119410A1Pulse-rejecting circuit for suppressing single-event transientsHONEYWELL INT INC·Filed 2004·Application pending·0 cites
- 1530US9799409B2Read-only memory (ROM) architecture with selective encodingAVAGO TECHNOLOGIES GENERAL IP·Filed 2016·Granted Oct 24, 2017·0 cites·22 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →