Inventor · disambiguated record
Robert L. Caulk, Jr.
Also filed as: CAULK JR ROBERT L · CAULK ROBERT LOUIS
10 granted patents·1 pending application·490 citations·filing 1991–2006
91Inventor score
Top patents by PatentIndex Score
11 records- 0192US5392391AHigh performance graphics applications controllerLSI LOGIC CORP·Filed 1991·Granted Feb 21, 1995·180 cites·3 claims
- 0288US7184662B2Switching networkBAY MICROSYSEMS INC·Filed 2001·Granted Feb 27, 2007·43 cites·19 claims
- 0383US6341324B1Exception processing in superscalar microprocessorLSI LOGIC CORP·Filed 1995·Granted Jan 22, 2002·119 cites·16 claims
- 0472US5742780ADual pipeline superscalar reduced instruction set computer system architectureLSI LOGIC CORP·Filed 1997·Granted Apr 21, 1998·58 cites·12 claims
- 0572US5603047ASuperscalar microprocessor architectureLSI LOGIC CORP·Filed 1995·Granted Feb 11, 1997·61 cites·10 claims
- 0663US7139291B2Hitless reconfiguration of a switching networkBAY MICROSYSTEMS INC·Filed 2002·Granted Nov 21, 2006·6 cites·12 claims
- 0761US7752398B2Multi-port memory architecture for storing multi-dimensional arrays ILSI CORP·Filed 2006·Granted Jul 6, 2010·2 cites·28 claims
- 0846US7707363B2Multi-port memory architecture for storing multi-dimensional arrays IILSI CORP·Filed 2006·Granted Apr 27, 2010·0 cites·20 claims
- 0944US2007274398A1Parallelization of Video Decoding on Single-Instruction, Multiple-Data ProcessorsMETTA TECHNOLOGY INC·Filed 2006·Application pending·0 cites
- 1039US5764939ARISC processor having coprocessor for executing circular mask instructionLSI LOGIC CORP·Filed 1995·Granted Jun 9, 1998·12 cites·6 claims
- 1136US5737562ACPU pipeline having queuing stage to facilitate branch instructionsLSI LOGIC CORP·Filed 1995·Granted Apr 7, 1998·9 cites·11 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →