Inventor · disambiguated record
Robert S. Chau
Also filed as: CHAU ROBERT · CHAU ROBERT S · CHAU ROBERT S K
495 granted patents·105 pending applications·17,771 citations·filing 1991–2024
99Inventor score
Top patents by PatentIndex Score
600 records- 0199US8987794B2Non-planar gate all-around device and method of fabrication thereofRACHMADY WILLY·Filed 2011·Granted Mar 24, 2015·65 cites·29 claims
- 0299US7662689B2Strained transistor integration for CMOSINTEL CORP·Filed 2003·Granted Feb 16, 2010·343 cites·34 claims
- 0399US7531437B2Method of forming metal gate electrodes using sacrificial gate electrode material and sacrificial gate dielectric materialINTEL CORP·Filed 2006·Granted May 12, 2009·195 cites·10 claims
- 0499US7518196B2Field effect transistor with narrow bandgap source and drain regions and method of fabricationINTEL CORP·Filed 2005·Granted Apr 14, 2009·72 cites·22 claims
- 0599US7485536B2Abrupt junction formation by atomic layer epitaxy of in situ delta doped dopant diffusion barriersINTEL CORP·Filed 2005·Granted Feb 3, 2009·155 cites·4 claims
- 0699US7241653B2Nonplanar device with stress incorporation layer and method of fabricationINTEL CORP·Filed 2005·Granted Jul 10, 2007·125 cites·30 claims
- 0799US7105390B2Nonplanar transistors with metal gate electrodesINTEL CORP·Filed 2003·Granted Sep 12, 2006·416 cites·36 claims
- 0899US6885084B2Semiconductor transistor having a stressed channelINTEL CORP·Filed 2003·Granted Apr 26, 2005·159 cites·12 claims
- 0999US6861318B2Semiconductor transistor having a stressed channelINTEL CORP·Filed 2003·Granted Mar 1, 2005·165 cites·11 claims
- 1099US6858478B2Tri-gate devices and methods of fabricationINTEL CORP·Filed 2003·Granted Feb 22, 2005·629 cites·3 claims
- 1199US6621131B2Semiconductor transistor having a stressed channelINTEL CORP·Filed 2001·Granted Sep 16, 2003·534 cites·20 claims
- 1298US9123567B2CMOS implementation of germanium and III-V nanowires and nanoribbons in gate-all-around architectureRADOSAVLJEVIC MARKO·Filed 2011·Granted Sep 1, 2015·66 cites·26 claims
- 1398US8890264B2Non-planar III-V field effect transistors with conformal metal gate electrode and nitrogen doping of gate dielectric interfaceDEWEY GILBERT·Filed 2012·Granted Nov 18, 2014·95 cites·13 claims
- 1498US8294180B2CMOS devices with a single work function gate electrode and method of fabricationDOYLE BRIAN S·Filed 2011·Granted Oct 23, 2012·37 cites·14 claims
- 1598US8283653B2Non-planar germanium quantum well devicesPILLARISETTY RAVI·Filed 2009·Granted Oct 9, 2012·47 cites·20 claims
- 1698US8110877B2Metal-insulator-semiconductor tunneling contacts having an insulative layer disposed between source/drain contacts and source/drain regionsMUKHERJEE NILOY·Filed 2008·Granted Feb 7, 2012·108 cites·15 claims
- 1798US7898041B2Block contact architectures for nanoscale channel transistorsINTEL CORP·Filed 2007·Granted Mar 1, 2011·113 cites·20 claims
- 1898US7893506B2Field effect transistor with narrow bandgap source and drain regions and method of fabricationINTEL CORP·Filed 2010·Granted Feb 22, 2011·35 cites·10 claims
- 1998US7569443B2Complementary metal oxide semiconductor integrated circuit using raised source drain and replacement metal gateINTEL CORP·Filed 2005·Granted Aug 4, 2009·72 cites·9 claims
- 2098US7547637B2Methods for patterning a semiconductor filmINTEL CORP·Filed 2005·Granted Jun 16, 2009·52 cites·8 claims
- 2198US7531393B2Non-planar MOS structure with a strained channel regionINTEL CORP·Filed 2006·Granted May 12, 2009·121 cites·3 claims
- 2298US7485503B2Dielectric interface for group III-V semiconductor deviceINTEL CORP·Filed 2005·Granted Feb 3, 2009·63 cites·13 claims
- 2398US7479421B2Process for integrating planar and non-planar CMOS transistors on a bulk substrate and article made therebyINTEL CORP·Filed 2005·Granted Jan 20, 2009·105 cites·2 claims
- 2498US7407847B2Stacked multi-gate transistor design and method of fabricationINTEL CORP·Filed 2006·Granted Aug 5, 2008·99 cites·19 claims
- 2598US7358121B2Tri-gate devices and methods of fabricationINTEL CORP·Filed 2002·Granted Apr 15, 2008·153 cites·15 claims
- 2698US7326656B2Method of forming a metal oxide dielectricINTEL CORP·Filed 2006·Granted Feb 5, 2008·456 cites·19 claims
- 2798US7279375B2Block contact architectures for nanoscale channel transistorsINTEL CORP·Filed 2005·Granted Oct 9, 2007·93 cites·12 claims
- 2898US7268058B2Tri-gate transistors and methods to fabricate sameINTEL CORP·Filed 2004·Granted Sep 11, 2007·164 cites·20 claims
- 2998US7193279B2Non-planar MOS structure with a strained channel regionINTEL CORP·Filed 2005·Granted Mar 20, 2007·76 cites·23 claims
- 3098US7170120B2Carbon nanotube energy well (CNEW) field effect transistorINTEL CORP·Filed 2005·Granted Jan 30, 2007·149 cites·15 claims
- 3198US7022559B2MOSFET gate electrodes having performance tuned work functions and methods of making sameINTEL CORP·Filed 2002·Granted Apr 4, 2006·216 cites·22 claims
- 3298US6909151B2Nonplanar device with stress incorporation layer and method of fabricationINTEL CORP·Filed 2003·Granted Jun 21, 2005·241 cites·31 claims
- 3398US6897098B2Method of fabricating an ultra-narrow channel semiconductor deviceINTEL CORP·Filed 2003·Granted May 24, 2005·226 cites·25 claims
- 3498US6696345B2Metal-gate electrode for CMOS transistor applicationsINTEL CORP·Filed 2002·Granted Feb 24, 2004·164 cites·13 claims
- 3597US9252275B2Non-planar gate all-around device and method of fabrication thereofINTEL CORP·Filed 2014·Granted Feb 2, 2016·20 cites·19 claims
- 3697US9240410B2Group III-N nanowire transistorsTHEN HAN WUI·Filed 2011·Granted Jan 19, 2016·25 cites·17 claims
- 3797US8952541B2Method of fabricating metal-insulator-semiconductor tunneling contacts using conformal deposition and thermal growth processesMUKHERJEE NILOY·Filed 2012·Granted Feb 10, 2015·36 cites·5 claims
- 3897US8765563B2Trench confined epitaxially grown device layer(s)PILLARISETTY RAVI·Filed 2012·Granted Jul 1, 2014·42 cites·9 claims
- 3997US8575596B2Non-planar germanium quantum well devicesPILLARISETTY RAVI·Filed 2012·Granted Nov 5, 2013·24 cites·14 claims
- 4097US8110458B2Fabrication of germanium nanowire transistorsJIN BEEN-YIH·Filed 2010·Granted Feb 7, 2012·51 cites·15 claims
- 4197US7851790B2Isolated Germanium nanowire on Silicon finINTEL CORP·Filed 2008·Granted Dec 14, 2010·43 cites·3 claims
- 4297US7821061B2Silicon germanium and germanium multigate and nanowire structures for logic and multilevel memory applicationsINTEL CORP·Filed 2007·Granted Oct 26, 2010·41 cites·5 claims
- 4397US7820513B2Nonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabricationINTEL CORP·Filed 2008·Granted Oct 26, 2010·81 cites·3 claims
- 4497US7550333B2Nonplanar device with thinned lower body portion and method of fabricationINTEL CORP·Filed 2006·Granted Jun 23, 2009·50 cites·15 claims
- 4597US7525160B2Multigate device with recessed strain regionsINTEL CORP·Filed 2005·Granted Apr 28, 2009·65 cites·14 claims
- 4697US7494862B2Methods for uniform doping of non-planar transistor structuresINTEL CORP·Filed 2006·Granted Feb 24, 2009·70 cites·10 claims
- 4797US7456476B2Nonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabricationINTEL CORP·Filed 2003·Granted Nov 25, 2008·222 cites·12 claims
- 4897US7355281B2Method for making semiconductor device having a high-k gate dielectric layer and a metal gate electrodeINTEL CORP·Filed 2006·Granted Apr 8, 2008·47 cites·12 claims
- 4997US7348284B2Non-planar pMOS structure with a strained channel region and an integrated strained CMOS flowINTEL CORP·Filed 2004·Granted Mar 25, 2008·141 cites·10 claims
- 5097US7226831B1Device with scavenging spacer layerINTEL CORP·Filed 2005·Granted Jun 5, 2007·60 cites·8 claims
Showing the top 50 of 600 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →