Inventor · disambiguated record
Robert N. Ehrlich
Also filed as: EHRLICH ROBERT · EHRLICH ROBERT N
10 granted patents·1 pending application·32 citations·filing 2006–2024
84Inventor score
Files withFREESCALE SEMICONDUCTOR INC3EHRLICH ROBERT2EHRLICH ROBERT N2DEOGHARIA AMAR NATH1LIM CHING SIA1
Top patents by PatentIndex Score
11 records- 0184US8601315B2Debugger recovery on exit from low power modeEHRLICH ROBERT·Filed 2010·Granted Dec 3, 2013·11 cites·25 claims
- 0280US9366724B1Scan testing with staggered clocksFREESCALE SEMICONDUCTOR INC·Filed 2014·Granted Jun 14, 2016·8 cites·20 claims
- 0372US7793025B2Hardware managed context sensitive interrupt priority level controlFREESCALE SEMICONDUCTOR INC·Filed 2008·Granted Sep 7, 2010·6 cites·20 claims
- 0466US9626279B2Debug method and device for providing indexed trace messagesMCGOWAN ROBERT A·Filed 2013·Granted Apr 18, 2017·2 cites·20 claims
- 0563US8666690B2Heterogeneous multi-core integrated circuit and method for debugging sameDEOGHARIA AMAR NATH·Filed 2011·Granted Mar 4, 2014·2 cites·20 claims
- 0662US2025123328A1Boundary Scan Power Up Voltage Level ConfigurationLIM CHING SIA·Filed 2024·Application pending·0 cites
- 0757US8572323B2Cache result register for quick cache information lookupEHRLICH ROBERT·Filed 2010·Granted Oct 29, 2013·1 cites·20 claims
- 0854US9304880B2System and method for multicore processingOLIVAREZ MICHAEL L·Filed 2013·Granted Apr 5, 2016·2 cites·20 claims
- 0944US9626280B2Debug method and device for handling exceptions and interruptsEHRLICH ROBERT N·Filed 2013·Granted Apr 18, 2017·0 cites·20 claims
- 1042US7747889B2Bus having a dynamic timing bridgeFREESCALE SEMICONDUCTOR INC·Filed 2006·Granted Jun 29, 2010·0 cites·18 claims
- 1138US9495169B2Predicate trace compressionEHRLICH ROBERT N·Filed 2012·Granted Nov 15, 2016·0 cites·19 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →