Inventor · disambiguated record
Roger Espasa
Also filed as: ESPASA ROGER
17 granted patents·13 pending applications·99 citations·filing 2005–2021
92Inventor score
Top patents by PatentIndex Score
30 records- 0193US7627735B2Implementing vector memory operationsINTEL CORP·Filed 2005·Granted Dec 1, 2009·45 cites·28 claims
- 0288US9785433B2Three source operand floating-point addition instruction with operand negation bits and intermediate and final result roundingINTEL CORP·Filed 2015·Granted Oct 10, 2017·10 cites·19 claims
- 0384US8533436B2Adaptively handling remote atomic execution based upon contention predictionFRYMAN JOSHUA B·Filed 2009·Granted Sep 10, 2013·17 cites·20 claims
- 0474US10445244B2Method, system, and apparatus for page sizing extensionINTEL CORP·Filed 2016·Granted Oct 15, 2019·1 cites·18 claims
- 0573US8707012B2Implementing vector memory operationsESPASA ROGER·Filed 2012·Granted Apr 22, 2014·3 cites·20 claims
- 0672US10445092B2Method and apparatus for performing a vector permute with an index and an immediateINTEL CORP·Filed 2014·Granted Oct 15, 2019·3 cites·21 claims
- 0771US2021374069A1Method, system, and apparatus for page sizing extensionINTEL CORP·Filed 2021·Application pending·0 cites
- 0870US8316216B2Implementing vector memory operationsESPASA ROGER·Filed 2009·Granted Nov 20, 2012·4 cites·20 claims
- 0969US9654143B2Consecutive bit error detection and correctionINTEL CORP·Filed 2014·Granted May 16, 2017·4 cites·15 claims
- 1067US9934155B2Method, system, and apparatus for page sizing extensionINTEL CORP·Filed 2012·Granted Apr 3, 2018·1 cites·14 claims
- 1166US9436468B2Technique for setting a vector maskESPASA ROGER·Filed 2005·Granted Sep 6, 2016·4 cites·20 claims
- 1265US9244855B2Method, system, and apparatus for page sizing extensionGROCHOWSKI ED·Filed 2007·Granted Jan 26, 2016·3 cites·20 claims
- 1365US2020242046A1Method, system, and apparatus for page sizing extensionINTEL CORP·Filed 2019·Application pending·0 cites
- 1464US9733935B2Super multiply add (super madd) instructionCORBAL JESUS·Filed 2011·Granted Aug 15, 2017·2 cites·21 claims
- 1560US9606931B2Indicating a length of an instruction of a variable length instruction setGALAN SANTIAGO·Filed 2011·Granted Mar 28, 2017·2 cites·18 claims
- 1659US10445245B2Method, system, and apparatus for page sizing extensionINTEL CORP·Filed 2016·Granted Oct 15, 2019·0 cites·16 claims
- 1757US2020097290A1Method and apparatus for performing a vector permute with an index and an immediateINTEL CORP·Filed 2019·Application pending·0 cites
- 1854US2021132950A1Bit shuffle processors, methods, systems, and instructionsINTEL CORP·Filed 2020·Application pending·0 cites
- 1951US2016283242A1Apparatus and method for vector horizontal logical instructionINTEL CORP·Filed 2014·Application pending·0 cites
- 2051US2019138303A1Apparatus and method for vector horizontal logical instructionINTEL CORP·Filed 2018·Application pending·0 cites
- 2150US10296489B2Method and apparatus for performing a vector bit shuffleINTEL CORP·Filed 2014·Granted May 21, 2019·0 cites·25 claims
- 2250US10296334B2Method and apparatus for performing a vector bit gatherINTEL CORP·Filed 2014·Granted May 21, 2019·0 cites·25 claims
- 2348US2018032332A1Three source operand floating-point addition instruction with operand negation bits and intermediate and final result roundingINTEL CORP·Filed 2017·Application pending·0 cites
- 2447US2016188341A1Apparatus and method for fused add-add instructionsOULD-AHMED-VALL ELMOUSTAPHA·Filed 2014·Application pending·0 cites
- 2547US2016188333A1Method and apparatus for compressing a mask valueINTEL CORP·Filed 2014·Application pending·0 cites
- 2647US2016188327A1Apparatus and method for fused multiply-multiply instructionsOULD-AHMED-VALL ELMOUSTAPHA·Filed 2014·Application pending·0 cites
- 2746US10713044B2Bit shuffle processors, methods, systems, and instructionsINTEL CORP·Filed 2015·Granted Jul 14, 2020·0 cites·23 claims
- 2844US2016179523A1Apparatus and method for vector broadcast and xorand logical instructionINTEL CORP·Filed 2014·Application pending·0 cites
- 2941US2015277904A1Method and apparatus for performing a plurality of multiplication operationsESPASA ROGER·Filed 2014·Application pending·0 cites
- 3032US2017308383A1Bit group interleave processors, methods, systems, and instructionsINTEL CORP·Filed 2015·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →