Inventor · disambiguated record
Romain H.A. Feuillette
Also filed as: FEUILLETTE ROMAIN · FEUILLETTE ROMAIN H A
6 granted patents·15 pending applications·0 citations·filing 2020–2025
64Inventor score
Files withGLOBALFOUNDRIES US INC21
Top patents by PatentIndex Score
21 records- 0172US12300627B1Integrated circuit structures having a watermarkGLOBALFOUNDRIES US INC·Filed 2024·Granted May 13, 2025·0 cites·8 claims
- 0264US2025391783A1Integrated circuit structures having a watermarkGLOBALFOUNDRIES US INC·Filed 2025·Application pending·0 cites
- 0362US12501624B1Memory device structures that include a capacitorGLOBALFOUNDRIES US INC·Filed 2024·Granted Dec 16, 2025·0 cites·20 claims
- 0462US11913971B2Motion-sensitive field effect transistor, motion detection system, and methodGLOBALFOUNDRIES US INC·Filed 2021·Granted Feb 27, 2024·0 cites·20 claims
- 0562US2024387668A1Nanosheet structures with tunable channels and inner sidewall spacersGLOBALFOUNDRIES US INC·Filed 2023·Application pending·0 cites
- 0661US12424493B2Self-aligned double patterning with mandrel manipulationGLOBALFOUNDRIES US INC·Filed 2022·Granted Sep 23, 2025·0 cites·20 claims
- 0758US12353817B2Pcell verificationGLOBALFOUNDRIES US INC·Filed 2022·Granted Jul 8, 2025·0 cites·20 claims
- 0856US2025254985A1Finfet with gate-all-around structure including gate dielectric layer thicker in buried gate region than in outer gate regionGLOBALFOUNDRIES US INC·Filed 2024·Application pending·0 cites
- 0954US2025356066A13d schematic visualizationGLOBALFOUNDRIES US INC·Filed 2024·Application pending·0 cites
- 1054US2025245410A1Method and system employing linear distance marker-based design layout analysisGLOBALFOUNDRIES US INC·Filed 2024·Application pending·0 cites
- 1154US2025241062A1Structure with two work function metals over conductive bridge, and method to form sameGLOBALFOUNDRIES US INC·Filed 2024·Application pending·0 cites
- 1253US2025040167A1Gate-all-around field effect transistorsGLOBALFOUNDRIES US INC·Filed 2023·Application pending·0 cites
- 1352US2025031439A1Fin-type field effect transistor with independently biasable supplementary gate and methodGLOBALFOUNDRIES US INC·Filed 2023·Application pending·0 cites
- 1452US2025173495A1Real-time process margin-based layout optimizationGLOBALFOUNDRIES US INC·Filed 2023·Application pending·0 cites
- 1551US2025006650A1Machine-readable code in integrated circuitGLOBALFOUNDRIES US INC·Filed 2023·Application pending·0 cites
- 1651US2024347638A1Multi-fin fin-type field effect transistor with fine-tuned effective channel widthGLOBALFOUNDRIES US INC·Filed 2023·Application pending·0 cites
- 1749US11722298B2Public-private encryption key generation using Pcell parameter values and on-chip physically unclonable function valuesGLOBALFOUNDRIES US INC·Filed 2020·Granted Aug 8, 2023·0 cites·20 claims
- 1849US2024370632A1Method for performing design rule checksGLOBALFOUNDRIES US INC·Filed 2023·Application pending·0 cites
- 1949US2024242013A1Trusted parameterized cells (pcells) on blockchainGLOBALFOUNDRIES US INC·Filed 2023·Application pending·0 cites
- 2049US2025148181A1Signal propagation simulation including photonic device-to-photonic device connectivity awarenessGLOBALFOUNDRIES US INC·Filed 2023·Application pending·0 cites
- 2147US2025238589A1Integrated circuit design method and system employing parasitic diode analysisGLOBALFOUNDRIES US INC·Filed 2024·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →