Inventor · disambiguated record
Robert Glen Gerowitz
Also filed as: GEROWITZ ROBERT G · GEROWITZ ROBERT GLEN
16 granted patents·216 citations·filing 1999–2020
91Inventor score
Top patents by PatentIndex Score
16 records- 0197US6222380B1High speed parallel/serial link for data communicationIBM·Filed 1999·Granted Apr 24, 2001·151 cites·25 claims
- 0279US6681356B1Scan chain connectivityIBM·Filed 2000·Granted Jan 20, 2004·31 cites·18 claims
- 0373US7506225B2Scanned memory testing of multi-port memory arraysIBM·Filed 2005·Granted Mar 17, 2009·7 cites·9 claims
- 0469US11016144B2Testing integrated circuit designs containing multiple phase rotatorsIBM·Filed 2020·Granted May 25, 2021·0 cites·20 claims
- 0561US10761136B2Testing integrated circuit designs containing multiple phase rotatorsIBM·Filed 2017·Granted Sep 1, 2020·0 cites·10 claims
- 0661US7768315B2Multiplexor with leakage power regulatorIBM·Filed 2007·Granted Aug 3, 2010·4 cites·8 claims
- 0760US8135571B2Validating manufacturing test rules pertaining to an electronic componentCASSANI CARISA ANNE·Filed 2008·Granted Mar 13, 2012·5 cites·17 claims
- 0856US10585140B2Testing integrated circuit designs containing multiple phase rotatorsIBM·Filed 2017·Granted Mar 10, 2020·0 cites·20 claims
- 0956US8065641B2Automatically creating manufacturing test rules pertaining to an electronic componentGEROWITZ ROBERT GLEN·Filed 2008·Granted Nov 22, 2011·2 cites·15 claims
- 1056US7646210B2Method and system for low-power level-sensitive scan design latch with power-gated logicIBM·Filed 2007·Granted Jan 12, 2010·3 cites·20 claims
- 1154US9927489B2Testing integrated circuit designs containing multiple phase rotatorsIBM·Filed 2014·Granted Mar 27, 2018·0 cites·18 claims
- 1252US7127691B2Method and apparatus for manufacturing test generationIBM·Filed 2004·Granted Oct 24, 2006·8 cites·36 claims
- 1344US8136059B2Indeterminate state logic insertionGEROWITZ ROBERT GLEN·Filed 2008·Granted Mar 13, 2012·0 cites·14 claims
- 1443US7865786B2Scanned memory testing of multi-port memory arraysIBM·Filed 2009·Granted Jan 4, 2011·0 cites·10 claims
- 1540US6519757B1Hardware design language generation for input/output logic levelIBM·Filed 2000·Granted Feb 11, 2003·0 cites·2 claims
- 1626US6407569B1Integrated circuit with in situ circuit arrangement for testing integrity of differential receiver inputsIBM·Filed 1999·Granted Jun 18, 2002·5 cites·12 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →