Inventor · disambiguated record
Roger Gramunt
Also filed as: GRAMUNT ROGER
19 granted patents·5 pending applications·80 citations·filing 2005–2025
92Inventor score
Top patents by PatentIndex Score
24 records- 0193US7627735B2Implementing vector memory operationsINTEL CORP·Filed 2005·Granted Dec 1, 2009·45 cites·28 claims
- 0292US10776699B2Optimized compute hardware for machine learning operationsINTEL CORP·Filed 2018·Granted Sep 15, 2020·10 cites·20 claims
- 0389US11334796B2Optimized compute hardware for machine learning operationsINTEL CORP·Filed 2020·Granted May 17, 2022·2 cites·62 claims
- 0482US2025362924A1Optimized compute hardware for machine learning operationsINTEL CORP·Filed 2025·Application pending·0 cites
- 0576US12314727B2Optimized compute hardware for machine learning operationsINTEL CORP·Filed 2022·Granted May 27, 2025·0 cites·20 claims
- 0675US10007620B2System and method for cache replacement using conservative set duelingINTEL CORP·Filed 2016·Granted Jun 26, 2018·2 cites·20 claims
- 0774US10445244B2Method, system, and apparatus for page sizing extensionINTEL CORP·Filed 2016·Granted Oct 15, 2019·1 cites·18 claims
- 0874US10175986B2Stateless capture of data linear addresses during precise event based samplingINTEL CORP·Filed 2017·Granted Jan 8, 2019·2 cites·20 claims
- 0973US8707012B2Implementing vector memory operationsESPASA ROGER·Filed 2012·Granted Apr 22, 2014·3 cites·20 claims
- 1071US2021374069A1Method, system, and apparatus for page sizing extensionINTEL CORP·Filed 2021·Application pending·0 cites
- 1170US8316216B2Implementing vector memory operationsESPASA ROGER·Filed 2009·Granted Nov 20, 2012·4 cites·20 claims
- 1267US9934155B2Method, system, and apparatus for page sizing extensionINTEL CORP·Filed 2012·Granted Apr 3, 2018·1 cites·14 claims
- 1366US9436468B2Technique for setting a vector maskESPASA ROGER·Filed 2005·Granted Sep 6, 2016·4 cites·20 claims
- 1465US9244855B2Method, system, and apparatus for page sizing extensionGROCHOWSKI ED·Filed 2007·Granted Jan 26, 2016·3 cites·20 claims
- 1565US2020242046A1Method, system, and apparatus for page sizing extensionINTEL CORP·Filed 2019·Application pending·0 cites
- 1662US9715432B2Memory fault suppression via re-execution and hardware FSMINTEL CORP·Filed 2014·Granted Jul 25, 2017·1 cites·16 claims
- 1760US9652237B2Stateless capture of data linear addresses during precise event based samplingGRAMUNT ROGER·Filed 2014·Granted May 16, 2017·2 cites·20 claims
- 1859US10445245B2Method, system, and apparatus for page sizing extensionINTEL CORP·Filed 2016·Granted Oct 15, 2019·0 cites·16 claims
- 1949US9804842B2Method and apparatus for efficiently managing architectural register state of a processorINTEL CORP·Filed 2014·Granted Oct 31, 2017·0 cites·20 claims
- 2048US2023195456A1System, apparatus and method for throttling fusion of micro-operations in a processorINTEL CORP·Filed 2021·Application pending·0 cites
- 2147US10719320B2Power noise injection to control rate of change of currentINTEL CORP·Filed 2017·Granted Jul 21, 2020·0 cites·20 claims
- 2245US9886396B2Scalable event handling in multi-threaded processor coresINTEL CORP·Filed 2014·Granted Feb 6, 2018·0 cites·15 claims
- 2337US9891914B2Method and apparatus for performing an efficient scatterMATAS RAMON·Filed 2015·Granted Feb 13, 2018·0 cites·25 claims
- 2426US2016378497A1Systems, Methods, and Apparatuses for Thread Selection and Reservation Station BindingGRAMUNT ROGER·Filed 2015·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →