Inventor · disambiguated record
Ronald P. Hall
Also filed as: HALL RONALD · HALL RONALD P
47 granted patents·4 pending applications·193 citations·filing 2003–2025
98Inventor score
Top patents by PatentIndex Score
51 records- 0191US11487667B1Prediction confirmation for cache subsystemAPPLE INC·Filed 2021·Granted Nov 1, 2022·2 cites·20 claims
- 0290US7401242B2Dynamic power management in a processor designIBM·Filed 2005·Granted Jul 15, 2008·22 cites·7 claims
- 0386US10901484B2Fetch predition circuit for reducing power consumption in a processorAPPLE INC·Filed 2019·Granted Jan 26, 2021·3 cites·20 claims
- 0486US7437539B2Issue unit for placing a processor into a gradual slow mode of operation in response to a detected livelock condition within a processor pipelineIBM·Filed 2006·Granted Oct 14, 2008·13 cites·10 claims
- 0585US7490224B2Time-of-life counter design for handling instruction flushes from a queueIBM·Filed 2005·Granted Feb 10, 2009·13 cites·3 claims
- 0683US11080188B1Method to ensure forward progress of a processor in the presence of persistent external cache/TLB maintenance requestsAPPLE INC·Filed 2018·Granted Aug 3, 2021·4 cites·20 claims
- 0783US10402326B1Accessing memories in coherent and non-coherent domains in a computing systemAPPLE INC·Filed 2016·Granted Sep 3, 2019·4 cites·19 claims
- 0883US8131980B2Structure for dynamic livelock resolution with variable delay memory access queueHALL RONALD·Filed 2008·Granted Mar 6, 2012·15 cites·17 claims
- 0982US7681056B2Dynamic power management in a processor designIBM·Filed 2008·Granted Mar 16, 2010·10 cites·7 claims
- 1081US8612730B2Hardware assist thread for dynamic performance profilingHALL RONALD P·Filed 2010·Granted Dec 17, 2013·7 cites·16 claims
- 1181US8423750B2Hardware assist thread for increasing code parallelismHALL RONALD P·Filed 2010·Granted Apr 16, 2013·6 cites·11 claims
- 1278US12481591B2Prediction confirmation for cache subsystemAPPLE INC·Filed 2024·Granted Nov 25, 2025·0 cites·20 claims
- 1378US10552323B1Cache flush method and apparatusAPPLE INC·Filed 2018·Granted Feb 4, 2020·2 cites·20 claims
- 1478US7434033B2Placing a processor into a gradual slow mode of operation in response to a detected livelock condition within a processor pipelineIBM·Filed 2006·Granted Oct 7, 2008·7 cites·11 claims
- 1577US9052910B2Efficiency of short loop instruction fetchHALL RONALD·Filed 2008·Granted Jun 9, 2015·9 cites·21 claims
- 1677US7461239B2Apparatus and method for handling data cache misses out-of-order for asynchronous pipelinesIBM·Filed 2006·Granted Dec 2, 2008·7 cites·23 claims
- 1776US8898441B2Obtaining and releasing hardware threads without hypervisor involvementFRAZIER GILES ROGER·Filed 2012·Granted Nov 25, 2014·4 cites·11 claims
- 1876US7900024B2Handling data cache misses out-of-order for asynchronous pipelinesIBM·Filed 2008·Granted Mar 1, 2011·6 cites·12 claims
- 1975US7818544B2Processor livelock recovery by gradual stalling of instruction processing rate during detection of livelock conditionIBM·Filed 2008·Granted Oct 19, 2010·5 cites·20 claims
- 2075US2025321744A1Using a Next Fetch Predictor Circuit with Short Branches and Return Fetch GroupsAPPLE INC·Filed 2025·Application pending·0 cites
- 2174US9037837B2Hardware assist thread for increasing code parallelismHALL RONALD P·Filed 2012·Granted May 19, 2015·3 cites·14 claims
- 2273US9524011B2Instruction loop buffer with tiered power savingsAPPLE INC·Filed 2014·Granted Dec 20, 2016·3 cites·20 claims
- 2373US7653848B2Selectively engaging optional data reduction mechanisms for capturing trace dataIBM·Filed 2006·Granted Jan 26, 2010·6 cites·20 claims
- 2472US11880308B2Prediction confirmation for cache subsystemAPPLE INC·Filed 2022·Granted Jan 23, 2024·0 cites·20 claims
- 2572US9395992B2Instruction swap for patching problematic instructions in a microprocessorIBM·Filed 2012·Granted Jul 19, 2016·4 cites·19 claims
- 2670US8200946B2Issue unit for placing a processor into a gradual slow mode of operationABERNATHY CHRISTOPHER M·Filed 2008·Granted Jun 12, 2012·4 cites·20 claims
- 2770US7913070B2Time-of-life counter for handling instruction flushes from a queueIBM·Filed 2008·Granted Mar 22, 2011·4 cites·2 claims
- 2869US10241557B2Reducing power consumption in a processorAPPLE INC·Filed 2013·Granted Mar 26, 2019·2 cites·20 claims
- 2969US7055004B2Pseudo-LRU for a locking cacheIBM·Filed 2003·Granted May 30, 2006·13 cites·24 claims
- 3067US9940262B2Immediate branch recode that handles aliasingAPPLE INC·Filed 2014·Granted Apr 10, 2018·2 cites·18 claims
- 3167US9632791B2Cache for patterns of instructions with multiple forward control transfersAPPLE INC·Filed 2014·Granted Apr 25, 2017·2 cites·18 claims
- 3267US9311098B2Mechanism for reducing cache power consumption using cache way predictionAPPLE INC·Filed 2013·Granted Apr 12, 2016·2 cites·20 claims
- 3367US7328330B2Queue design supporting dependency checking and issue for SIMD instructions within a general purpose processorIBM·Filed 2005·Granted Feb 5, 2008·3 cites·1 claims
- 3465US12373215B2Using a next fetch predictor circuit with short branches and return fetch groupsAPPLE INC·Filed 2022·Granted Jul 29, 2025·0 cites·20 claims
- 3564US9395995B2Retrieving instructions of a single branch, backwards short loop from a virtual loop bufferHALL RONALD·Filed 2012·Granted Jul 19, 2016·1 cites·16 claims
- 3664US8028151B2Performance of an in-order processor by no longer requiring a uniform completion point across different execution pipelinesIBM·Filed 2008·Granted Sep 27, 2011·2 cites·13 claims
- 3763US7516275B2Pseudo-LRU virtual counter for a locking cacheIBM·Filed 2006·Granted Apr 7, 2009·3 cites·3 claims
- 3861US12265823B2Trace cache with filter for internal control transfer inclusionAPPLE INC·Filed 2023·Granted Apr 1, 2025·0 cites·20 claims
- 3955US9632788B2Buffering instructions of a single branch, backwards short loop within a virtual loop bufferIBM·Filed 2016·Granted Apr 25, 2017·0 cites·20 claims
- 4054US11893413B2Virtual channel support using write tableAPPLE INC·Filed 2021·Granted Feb 6, 2024·0 cites·20 claims
- 4154US8719554B2Scaleable status tracking of multiple assist hardware threadsIBM·Filed 2013·Granted May 6, 2014·0 cites·10 claims
- 4252US7831808B2Queue design system supporting dependency checking and issue for SIMD instructions within a general purpose processorIBM·Filed 2007·Granted Nov 9, 2010·0 cites·12 claims
- 4351US9772851B2Retrieving instructions of a single branch, backwards short loop from a local loop buffer or virtual loop bufferHALL RONALD·Filed 2007·Granted Sep 26, 2017·0 cites·18 claims
- 4449US8713290B2Scaleable status tracking of multiple assist hardware threadsARNDT RICHARD LOUIS·Filed 2010·Granted Apr 29, 2014·0 cites·10 claims
- 4548US7900027B2Scalable link stack control method with full support for speculative operationsIBM·Filed 2008·Granted Mar 1, 2011·0 cites·15 claims
- 4648US7475232B2Performance of an in-order processor by no longer requiring a uniform completion point across different execution pipelinesIBM·Filed 2005·Granted Jan 6, 2009·0 cites·10 claims
- 4746US8793474B2Obtaining and releasing hardware threads without hypervisor involvementFRAZIER GILES ROGER·Filed 2010·Granted Jul 29, 2014·0 cites·11 claims
- 4846US7558921B2Method for data set replacement in 4-way or greater locking cacheIBM·Filed 2005·Granted Jul 7, 2009·0 cites·20 claims
- 4944US2008016408A1System and Method for Streaming High Frequency Trace Data Off-ChipABERNATHY CHRISTOPHER M·Filed 2006·Application pending·0 cites
- 5043US2008065873A1Dynamic livelock resolution with variable delay memory access queueHALL RONALD·Filed 2006·Application pending·0 cites
Showing the top 50 of 51 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →