Inventor · disambiguated record
Romain Jaillet
Also filed as: JAILLET ROMAIN
2 granted patents·0 citations·filing 2019–2021
28Inventor score
Technology areasH10P
Files withST MICROELECTRONICS TOURS SAS2
Top patents by PatentIndex Score
2 records- 0161US11784104B2Method of forming electronic chip package having a conductive layer between a chip and a supportST MICROELECTRONICS TOURS SAS·Filed 2021·Granted Oct 10, 2023·0 cites·19 claims
- 0253US11158556B2Electronic chip package having a support and a conductive layer on the supportST MICROELECTRONICS TOURS SAS·Filed 2019·Granted Oct 26, 2021·0 cites·19 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →