Inventor · disambiguated record
Romesh Mangho Jessani
Also filed as: JESSANI ROMESH MANGHO
10 granted patents·1 pending application·210 citations·filing 1996–2005
91Inventor score
Technology areasG06F
Top patents by PatentIndex Score
11 records- 0185US7739469B2Patching ROM codeFREESCALE SEMICONDUCTOR INC·Filed 2005·Granted Jun 15, 2010·17 cites·20 claims
- 0262US5913054AMethod and system for processing a multiple-register instruction that permit multiple data words to be written in a single processor cycleIBM·Filed 1996·Granted Jun 15, 1999·45 cites·8 claims
- 0357US5737749AMethod and system for dynamically sharing cache capacity in a microprocessorIBM·Filed 1996·Granted Apr 7, 1998·40 cites·16 claims
- 0455US5737751ACache memory management system having reduced reloads to a second level cache for enhanced memory performance in a data processing systemIBM·Filed 1996·Granted Apr 7, 1998·29 cites·8 claims
- 0550US5872948AProcessor and method for out-of-order execution of instructions based upon an instruction parameterIBM·Filed 1996·Granted Feb 16, 1999·23 cites·24 claims
- 0645US5812812AMethod and system of implementing an early data dependency resolution mechanism in a high-performance data processing system utilizing out-of-order instruction issueIBM·Filed 1996·Granted Sep 22, 1998·19 cites·8 claims
- 0745US5787479AMethod and system for preventing information corruption in a cache memory caused by an occurrence of a bus error during a linefill operationIBM·Filed 1996·Granted Jul 28, 1998·17 cites·11 claims
- 0840US2007083713A1System on a chip integrated circuit, processing system and methods for use therewithTORRINI ANTONIO·Filed 2005·Application pending·0 cites
- 0938US5805916AMethod and apparatus for dynamic allocation of registers for intermediate floating-point resultsIBM·Filed 1996·Granted Sep 8, 1998·10 cites·13 claims
- 1034US5870577ASystem and method for dispatching two instructions to the same execution unit in a single cycleIBM·Filed 1996·Granted Feb 9, 1999·7 cites·20 claims
- 1131US5764940AProcessor and method for executing a branch instruction and an associated target instruction utilizing a single instruction fetchIBM·Filed 1996·Granted Jun 9, 1998·3 cites·18 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →