Inventor · disambiguated record
Roland T. Knaack
Also filed as: KNAACK ROLAND · KNAACK ROLAND T · KNAACK ROLAND THOMAS
25 granted patents·1 pending application·517 citations·filing 1995–2025
97Inventor score
Files withCYPRESS SEMICONDUCTOR CORP13INTEGRATED DEVICE TECH11CYPRESS SEMICONDCUTOR CORP1MONTAGE TECH KUNSHAN CO LTD1
Top patents by PatentIndex Score
26 records- 0193US7079446B2DRAM interface circuits having enhanced skew, slew rate and impedance controlINTEGRATED DEVICE TECH·Filed 2004·Granted Jul 18, 2006·90 cites·21 claims
- 0288US6173425B1Methods of testing integrated circuits to include data traversal path identification information and related status information in test data streamsINTEGRATED DEVICE TECH·Filed 1998·Granted Jan 9, 2001·77 cites·43 claims
- 0383US9793708B1Overvoltage protection circuits and methods of operating sameINTEGRATED DEVICE TECH·Filed 2014·Granted Oct 17, 2017·6 cites·18 claims
- 0481US5978307AIntegrated circuit memory devices having partitioned multi-port memory arrays therein for increasing data bandwidth and methods of operating sameINTEGRATED DEVICE TECH·Filed 1998·Granted Nov 2, 1999·47 cites·43 claims
- 0576US5777944ACircuit and method for instruction controllable slewrate of bit line driverCYPRESS SEMICONDUCTOR CORP·Filed 1996·Granted Jul 7, 1998·33 cites·12 claims
- 0674US5642318ATesting method for FIFOSCYPRESS SEMICONDCUTOR CORP·Filed 1995·Granted Jun 24, 1997·46 cites·16 claims
- 0769US7082071B2Integrated DDR/SDR flow control managers that support multiple queues and MUX, DEMUX and broadcast operating modesINTEGRATED DEVICE TECH·Filed 2004·Granted Jul 25, 2006·16 cites·11 claims
- 0868US10565144B2Double data rate controllers and data buffers with support for multiple data widths of DRAMINTEGRATED DEVICE TECH·Filed 2018·Granted Feb 18, 2020·2 cites·20 claims
- 0967US6977539B1Clock signal generators having programmable full-period clock skew control and methods of generating clock signals having programmable skewsINTEGRATED DEVICE TECH·Filed 2003·Granted Dec 20, 2005·15 cites·17 claims
- 1065US7151398B2Clock signal generators having programmable full-period clock skew controlINTEGRATED DEVICE TECH·Filed 2005·Granted Dec 19, 2006·6 cites·9 claims
- 1163US6005821ACircuit and method for instruction controllable slew rate of bit line driverCYPRESS SEMICONDUCTOR CORP·Filed 1997·Granted Dec 21, 1999·15 cites·6 claims
- 1263US2025377800A1Memory system, computer system and data interaction methodMONTAGE TECH KUNSHAN CO LTD·Filed 2025·Application pending·0 cites
- 1361US10956349B2Support for multiple widths of DRAM in double data rate controllers or data buffersINTEGRATED DEVICE TECH·Filed 2019·Granted Mar 23, 2021·0 cites·20 claims
- 1461US5872802AParity generation and check circuit and method in read data pathCYPRESS SEMICONDUCTOR CORP·Filed 1996·Granted Feb 16, 1999·38 cites·20 claims
- 1558US7196562B1Programmable clock drivers that support CRC error checking of configuration data during program restore operationsINTEGRATED DEVICE TECH·Filed 2004·Granted Mar 27, 2007·10 cites·20 claims
- 1658US5682356AMultiple word width memory array clocking scheme for reading words from a memory arrayCYPRESS SEMICONDUCTOR CORP·Filed 1996·Granted Oct 28, 1997·15 cites·15 claims
- 1757US6023777ATesting method for devices with status flagsCYPRESS SEMICONDUCTOR CORP·Filed 1996·Granted Feb 8, 2000·16 cites·20 claims
- 1853US5968190ARedundancy method and circuit for self-repairing memory arraysCYPRESS SEMICONDUCTOR CORP·Filed 1996·Granted Oct 19, 1999·14 cites·20 claims
- 1952US7120075B1Multi-FIFO integrated circuit devices that support multi-queue operating modes with enhanced write path and read path queue switchingINTEGRATED DEVICE TECH·Filed 2004·Granted Oct 10, 2006·2 cites·16 claims
- 2051US5898315AOutput buffer circuit and method having improved accessCYPRESS SEMICONDUCTOR CORP·Filed 1996·Granted Apr 27, 1999·11 cites·22 claims
- 2148US5852748AProgrammable read-write word line equality signal generation for FIFOsCYPRESS SEMICONDUCTOR CORP·Filed 1995·Granted Dec 22, 1998·20 cites·13 claims
- 2244US5764967AMultiple frequency memory array clocking scheme for reading and writing multiple width digital wordsCYPRESS SEMICONDUCTOR CORP·Filed 1996·Granted Jun 9, 1998·17 cites·24 claims
- 2341US5712820AMultiple word width memory array clocking schemeCYPRESS SEMICONDUCTOR CORP·Filed 1995·Granted Jan 27, 1998·11 cites·20 claims
- 2435US5828617AMultiple word width memory array clocking scheme for reading words from a memory arrayCYPRESS SEMICONDUCTOR CORP·Filed 1997·Granted Oct 27, 1998·3 cites·15 claims
- 2533US6510486B1Clocking scheme for independently reading and writing multiple width words from a memory arrayCYPRESS SEMICONDUCTOR CORP·Filed 1996·Granted Jan 21, 2003·5 cites·15 claims
- 2630US5812465ARedundancy circuit and method for providing word lines driven by a shift registerCYPRESS SEMICONDUCTOR CORP·Filed 1996·Granted Sep 22, 1998·2 cites·15 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →