Inventor · disambiguated record
Ronny Meir Krashinsky
Also filed as: KRASHINSKY RONNY · KRASHINSKY RONNY M · KRASHINSKY RONNY MEIR
22 granted patents·26 pending applications·90 citations·filing 2011–2025
93Inventor score
Top patents by PatentIndex Score
48 records- 0194US11392829B1Managing data sparsity for neural networksNVIDIA CORP·Filed 2019·Granted Jul 19, 2022·35 cites·20 claims
- 0292US9093135B2System, method, and computer program product for implementing a storage arrayNVIDIA CORP·Filed 2012·Granted Jul 28, 2015·25 cites·20 claims
- 0391US12141082B2Method and apparatus for efficient access to multidimensional data structures and/or other large data blocksNVIDIA CORP·Filed 2022·Granted Nov 12, 2024·4 cites·25 claims
- 0491US12020035B2Programmatically controlled data multicasting across multiple compute enginesNVIDIA CORP·Filed 2022·Granted Jun 25, 2024·3 cites·21 claims
- 0584US12499052B2Method and apparatus for efficient access to multidimensional data structures and/or other large data blocksNVIDIA CORP·Filed 2022·Granted Dec 16, 2025·1 cites·16 claims
- 0681US11803380B2High performance synchronization mechanisms for coordinating operations on a computer systemNVIDIA CORP·Filed 2019·Granted Oct 31, 2023·2 cites·22 claims
- 0780US10459861B2Unified cache for diverse memory trafficNVIDIA CORP·Filed 2017·Granted Oct 29, 2019·2 cites·21 claims
- 0879US9830156B2Temporal SIMT execution optimization through elimination of redundant operationsKRASHINSKY RONNY M·Filed 2011·Granted Nov 28, 2017·8 cites·26 claims
- 0977US2024169472A1Storage of transformed tensor in a cacheNVIDIA CORP·Filed 2022·Application pending·0 cites
- 1077US2024169469A1Application programming interface to transform information corresponding to a memory transactionNVIDIA CORP·Filed 2022·Application pending·0 cites
- 1177US2024168659A1Application programming interface to transform and store information corresponding to a memory transactionNVIDIA CORP·Filed 2022·Application pending·0 cites
- 1277US2024168765A1Storage of tensor in a cacheNVIDIA CORP·Filed 2022·Application pending·0 cites
- 1377US2024168831A1Application programming interface to translate a tensor according to a tensor mapNVIDIA CORP·Filed 2022·Application pending·0 cites
- 1477US2024169471A1Storage of information in a graphics processing unit cacheNVIDIA CORP·Filed 2022·Application pending·0 cites
- 1577US2024168830A1Application programming interface to indicate storage locationsNVIDIA CORP·Filed 2022·Application pending·0 cites
- 1676US2024168829A1Application programming interface to generate a tensor mappingNVIDIA CORP·Filed 2022·Application pending·0 cites
- 1776US2024169470A1Application programming interface to store information in a plurality of storage locationsNVIDIA CORP·Filed 2022·Application pending·0 cites
- 1876US2024161223A1Application programming interface to translate a tensorNVIDIA CORP·Filed 2022·Application pending·0 cites
- 1976US2024161224A1Application programming interface to generate a tensor according to a tensor mapNVIDIA CORP·Filed 2022·Application pending·0 cites
- 2076US2025383879A1Scalarization of instructions for simt architecturesNVIDIA CORP·Filed 2025·Application pending·0 cites
- 2176US2024161222A1Application programming interface to indicate image-to-column transformationNVIDIA CORP·Filed 2022·Application pending·0 cites
- 2275US9971699B2Method to control cache replacement for decoupled data fetchNVIDIA CORP·Filed 2016·Granted May 15, 2018·2 cites·20 claims
- 2373US10067768B2Execution of divergent threads using a convergence barrierNVIDIA CORP·Filed 2015·Granted Sep 4, 2018·2 cites·20 claims
- 2472US9323679B2System, method, and computer program product for managing cache miss requestsKHAILANY BRUCEK KURDO·Filed 2012·Granted Apr 26, 2016·4 cites·19 claims
- 2572US2025272107A1Cooperative Group ArraysNVIDIA CORP·Filed 2025·Application pending·0 cites
- 2668US2025335196A1Application programming interface to wait on matrix multiply-accumulateNVIDIA CORP·Filed 2024·Application pending·0 cites
- 2767US12405801B2Scalarization of instructions for SIMT architecturesNVIDIA CORP·Filed 2023·Granted Sep 2, 2025·0 cites·20 claims
- 2866US12333311B2Cooperative group arraysNVIDIA CORP·Filed 2022·Granted Jun 17, 2025·0 cites·20 claims
- 2966US12248788B2Distributed shared memoryNVIDIA CORP·Filed 2022·Granted Mar 11, 2025·0 cites·24 claims
- 3066US11347668B2Unified cache for diverse memory trafficNVIDIA CORP·Filed 2020·Granted May 31, 2022·0 cites·20 claims
- 3165US12204897B2Application programming interface to wait on matrix multiply-accumulateNVIDIA CORP·Filed 2022·Granted Jan 21, 2025·0 cites·20 claims
- 3265US2025173152A1Distributed Shared MemoryNVIDIA CORP·Filed 2025·Application pending·0 cites
- 3364US11379420B2Decompression techniques for processing compressed data suitable for artificial neural networksNVIDIA CORP·Filed 2019·Granted Jul 5, 2022·1 cites·22 claims
- 3462US12449473B2Virtualizing hardware processing resources in a processorNVIDIA CORP·Filed 2022·Granted Oct 21, 2025·0 cites·12 claims
- 3559US12450683B2Application programming interface to provide informationNVIDIA CORP·Filed 2022·Granted Oct 21, 2025·0 cites·20 claims
- 3659US9292265B2Method for convergence analysis based on thread variance analysisGROVER VINOD·Filed 2012·Granted Mar 22, 2016·1 cites·20 claims
- 3757US10705994B2Unified cache for diverse memory trafficNVIDIA CORP·Filed 2017·Granted Jul 7, 2020·0 cites·20 claims
- 3852US2023110438A1Neural network data replacementNVIDIA CORP·Filed 2021·Application pending·0 cites
- 3952US2025272157A1Programmatic Work Assignment For Dynamically Load-Balanced Persistent ExecutionNVIDIA CORP·Filed 2024·Application pending·0 cites
- 4051US2025060938A1Method and apparatus for direct convolution calculationNVIDIA CORP·Filed 2023·Application pending·0 cites
- 4150US12340259B2Thread synchronization across memory synchronization domainsNVIDIA CORP·Filed 2021·Granted Jun 24, 2025·0 cites·20 claims
- 4247US2023289398A1Efficient Matrix Multiply and Add with a Group of WarpsNVIDIA CORP·Filed 2022·Application pending·0 cites
- 4347US2023297426A1Reconfiguring register and shared memory usage in thread arraysNVIDIA CORP·Filed 2022·Application pending·0 cites
- 4445US2023236878A1Efficiently launching tasks on a processorNVIDIA CORP·Filed 2022·Application pending·0 cites
- 4544US2023289212A1Flexible Migration of Executing Software Between Processing Components Without Need For Hardware ResetNVIDIA CORP·Filed 2022·Application pending·0 cites
- 4643US2023289211A1Techniques for Scalable Load Balancing of Thread Groups in a ProcessorNVIDIA CORP·Filed 2022·Application pending·0 cites
- 4742US2023315655A1Fast data synchronization in processors and memoryNVIDIA CORP·Filed 2022·Application pending·0 cites
- 4840US2022365882A1System and method of controlling cache memory residencyNVIDIA CORP·Filed 2021·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →