Inventor · disambiguated record
Ross Boyd Leavens
Also filed as: LEAVENS ROSS B · LEAVENS ROSS BOYD
20 granted patents·2 pending applications·715 citations·filing 1998–2015
95Inventor score
Top patents by PatentIndex Score
22 records- 0197US6829697B1Multiple logical interfaces to a shared coprocessor resourceIBM·Filed 2000·Granted Dec 7, 2004·168 cites·27 claims
- 0296US6775284B1Method and system for frame and protocol classificationIBM·Filed 2000·Granted Aug 10, 2004·143 cites·25 claims
- 0394US6931641B1Controller for multiple instruction thread processorsIBM·Filed 2000·Granted Aug 16, 2005·97 cites·11 claims
- 0488US7093109B1Network processor which makes thread execution control decisions based on latency event lengthsIBM·Filed 2000·Granted Aug 15, 2006·58 cites·11 claims
- 0587US6588008B1Assembler tool for processor-coprocessor computer systemsIBM·Filed 2000·Granted Jul 1, 2003·51 cites·14 claims
- 0686US7853912B2Arrangements for developing integrated circuit designsIBM·Filed 2007·Granted Dec 14, 2010·25 cites·17 claims
- 0781US7089555B2Ordered semaphore management subsystemIBM·Filed 2002·Granted Aug 8, 2006·33 cites·23 claims
- 0874US9448846B2Dynamically configurable hardware queues for dispatching jobs to a plurality of hardware acceleration enginesBASS BRIAN MITCHELL·Filed 2011·Granted Sep 20, 2016·3 cites·13 claims
- 0972US7143414B2Method and apparatus for locking multiple semaphoresIBM·Filed 2002·Granted Nov 28, 2006·18 cites·10 claims
- 1069US6769033B1Network processor processing complex and methodsIBM·Filed 1999·Granted Jul 27, 2004·67 cites·27 claims
- 1166US8006244B2Controller for multiple instruction thread processorsIBM·Filed 2004·Granted Aug 23, 2011·9 cites·27 claims
- 1261US7406690B2Flow lookahead in an ordered semaphore management subsystemIBM·Filed 2002·Granted Jul 29, 2008·7 cites·12 claims
- 1359US7440417B2Method and system for frame and protocol classificationIBM·Filed 2004·Granted Oct 21, 2008·4 cites·23 claims
- 1458US7917908B2Flow lookahead in an ordered semaphore management subsystemIBM·Filed 2008·Granted Mar 29, 2011·1 cites·8 claims
- 1555US9606838B2Dynamically configurable hardware queues for dispatching jobs to a plurality of hardware acceleration enginesIBM·Filed 2015·Granted Mar 28, 2017·0 cites·4 claims
- 1654US9710310B2Dynamically configurable hardware queues for dispatching jobs to a plurality of hardware acceleration enginesIBM·Filed 2015·Granted Jul 18, 2017·0 cites·3 claims
- 1753US6785278B1Methods, systems and computer program products for hashing address valuesIBM·Filed 1998·Granted Aug 31, 2004·31 cites·37 claims
- 1847US9286129B2Termination of requests in a distributed coprocessor systemIBM·Filed 2013·Granted Mar 15, 2016·0 cites·13 claims
- 1946US2005033938A1Network processing system, core language processor and method of executing a sequence of instructions in a stored programIBM·Filed 2004·Application pending·0 cites
- 2045US8230117B2Techniques for write-after-write ordering in a coherency managed processor system that employs a command pipelineDALY JR GEORGE WILLIAM·Filed 2009·Granted Jul 24, 2012·0 cites·20 claims
- 2142US7454753B2Semaphore management subsystem for use with multi-thread processor systemsIBM·Filed 2002·Granted Nov 18, 2008·0 cites·14 claims
- 2241US2013304990A1Dynamic Control of Cache Injection Based on Write Data TypeBASS BRIAN MITCHELL·Filed 2012·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →