Inventor · disambiguated record
Robert M. R. Neff
Also filed as: NEFF ROBERT · NEFF ROBERT M · NEFF ROBERT M R
9 granted patents·1 pending application·159 citations·filing 1999–2023
89Inventor score
Top patents by PatentIndex Score
10 records- 0195US7148828B2System and method for timing calibration of time-interleaved data convertersAGILENT TECHNOLOGIES INC·Filed 2005·Granted Dec 12, 2006·58 cites·22 claims
- 0291US11549973B1System for measuring voltage using pulse width modulator or voltage controlled oscillatorKEYSIGHT TECHNOLOGIES INC·Filed 2021·Granted Jan 10, 2023·2 cites·20 claims
- 0385US12231126B1System and method for generating sampling strobe for sampling an input signalKEYSIGHT TECHNOLOGIES INC·Filed 2023·Granted Feb 18, 2025·1 cites·20 claims
- 0480US6720895B2Method of calibrating an analog-to-digital converter and a circuit implementing the sameAGILENT TECHNOLOGIES INC·Filed 2002·Granted Apr 13, 2004·28 cites·15 claims
- 0577US6707411B1Analog-to-digital converter with on-chip memoryAGILENT TECHNOLOGIES INC·Filed 2002·Granted Mar 16, 2004·28 cites·25 claims
- 0669US6956423B2Interleaved clock signal generator having serial delay and ring counter architectureAGILENT TECHNOLOGIES INC·Filed 2002·Granted Oct 18, 2005·16 cites·25 claims
- 0758US6933862B2Power consumption stabilization system and methodAGILENT TECHNOLOGIES INC·Filed 2003·Granted Aug 23, 2005·6 cites·4 claims
- 0856US6909310B2CMOS controlled-impedance transmission line driverAGILENT TECHNOLOGIES INC·Filed 2003·Granted Jun 21, 2005·4 cites·20 claims
- 0950US6259281B1Parallel analog sampling circuit and analog-to-digital converter system incorporating clock signal generator generating sub-sampling clock signals with fast and precisely-timed edgesAGILENT TECHNOLOGIES INC·Filed 1999·Granted Jul 10, 2001·16 cites·14 claims
- 1029US2007002893A1Input/output (I/O) interface for high-speed data convertersNEFF ROBERT M R·Filed 2005·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →