Inventor · disambiguated record
Ronald Pasqualini
Also filed as: PASQUALINI RONALD
29 granted patents·1 pending application·640 citations·filing 1994–2008
97Inventor score
Top patents by PatentIndex Score
30 records- 0193US6690555B1Electrostatic discharge protection circuit with cascoded trigger-switch suitable for use with over-voltage tolerant CMOS input/output buffersNAT SEMICONDUCTOR CORP·Filed 2001·Granted Feb 10, 2004·79 cites·20 claims
- 0291US7388414B1Wideband power-on reset circuit with glitch-free outputNAT SEMICONDUCTOR CORP·Filed 2007·Granted Jun 17, 2008·20 cites·20 claims
- 0390US6489825B1High speed, low power, minimal area double edge triggered flip flopNAT SEMICONDUCTOR CORP·Filed 2001·Granted Dec 3, 2002·41 cites·18 claims
- 0488US7265599B1Flipflop that can tolerate arbitrarily slow clock edgesNAT SEMICONDUCTOR CORP·Filed 2004·Granted Sep 4, 2007·34 cites·27 claims
- 0587US7518419B1Wideband power-on reset circuitNAT SEMICONDUCTOR CORP·Filed 2006·Granted Apr 14, 2009·15 cites·14 claims
- 0686US7038898B1ESD protection circuit that can tolerate a negative input voltage during normal (non-ESD) operationNAT SEMICONDUCTOR CORP·Filed 2005·Granted May 2, 2006·13 cites·12 claims
- 0786US5428303ABias generator for low ground bounce output driverNAT SEMICONDUCTOR CORP·Filed 1994·Granted Jun 27, 1995·46 cites·7 claims
- 0884US7978454B1ESD structure that protects against power-on and power-off ESD eventNAT SEMICONDUCTOR CORP·Filed 2007·Granted Jul 12, 2011·13 cites·20 claims
- 0981US6380770B1Low ground bounce and low power supply bounce output driver with dual, interlocked, asymmetric delay linesNAT SEMICONDUCTOR CORP·Filed 2000·Granted Apr 30, 2002·25 cites·28 claims
- 1080US6160428AUniversal on-chip initialization circuitNAT SEMICONDUCTOR CORP·Filed 1998·Granted Dec 12, 2000·38 cites·17 claims
- 1176US6184729B1Low ground bounce and low power supply bounce output driverNAT SEMICONDUCTOR CORP·Filed 1998·Granted Feb 6, 2001·31 cites·15 claims
- 1276US5633606AScan flip-flop that holds state during shiftingNAT SEMICONDUCTOR CORP·Filed 1995·Granted May 27, 1997·38 cites·6 claims
- 1375US7996805B2Method of stitching scan flipflops together to form a scan chain with a reduced wire lengthNAT SEMICONDUCTOR CORP·Filed 2008·Granted Aug 9, 2011·7 cites·18 claims
- 1474US7723792B1Floating diodesNAT SEMICONDUCTOR CORP·Filed 2005·Granted May 25, 2010·5 cites·11 claims
- 1573US7098706B1High speed synchronizer for simultaneously initializing rising edge triggered and falling edge triggered flip-flopsNAT SEMICONDUCTOR CORP·Filed 2004·Granted Aug 29, 2006·17 cites·23 claims
- 1673US7042267B1Gated clock circuit with a substantially increased control signal delayNAT SEMICONDUCTOR CORP·Filed 2004·Granted May 9, 2006·18 cites·20 claims
- 1771US6492855B1Flip flop which has complementary, symmetric, minimal timing skew outputsNAT SEMICONDUCTOR CORP·Filed 2001·Granted Dec 10, 2002·15 cites·26 claims
- 1870US7185042B1High speed, universal polarity full adder which consumes minimal power and minimal areaNAT SEMICONDUCTOR CORP·Filed 2001·Granted Feb 27, 2007·15 cites·23 claims
- 1970US6397374B1Zero hold time circuit for high speed bus applicationsNAT SEMICONDUCTOR CORP·Filed 1998·Granted May 28, 2002·23 cites·30 claims
- 2069US7260808B1Method and metric for low power standard cell logic synthesisNAT SEMICONDUCTOR CORP·Filed 2004·Granted Aug 21, 2007·13 cites·20 claims
- 2169US5623223AGlitchless clock switching circuitNAT SEMICONDUCTOR CORP·Filed 1996·Granted Apr 22, 1997·70 cites·13 claims
- 2267US7863962B2High voltage CMOS output buffer constructed from low voltage CMOS transistorsNAT SEMICONDUCTOR CORP·Filed 2008·Granted Jan 4, 2011·5 cites·19 claims
- 2364US6104588ALow noise electrostatic discharge protection circuit for mixed signal CMOS integrated circuitsNAT SEMICONDUCTOR CORP·Filed 1998·Granted Aug 15, 2000·24 cites·25 claims
- 2462US6710432B1Integrated circuit package with low inductance ground path and improved thermal capabilityNAT SEMICONDUCTOR CORP·Filed 2001·Granted Mar 23, 2004·10 cites·8 claims
- 2559US6981013B1Low power, minimal area tap multiplierNAT SEMICONDUCTOR CORP·Filed 2001·Granted Dec 27, 2005·6 cites·22 claims
- 2655US7633311B2PECL/LVPECL input buffer that employs positive feedback to provide input hysteresis, symmetric headroom, and high noise immunityNAT SEMICONDUCTOR CORP·Filed 2008·Granted Dec 15, 2009·2 cites·19 claims
- 2754US7424507B1High speed, low power, pipelined zero crossing detector that utilizes carry save addersNAT SEMICONDUCTOR CORP·Filed 2004·Granted Sep 9, 2008·3 cites·22 claims
- 2852US6977420B2ESD protection circuit utilizing floating lateral clamp diodesNAT SEMICONDUCTOR CORP·Filed 1998·Granted Dec 20, 2005·11 cites·38 claims
- 2947US7109747B1Low power, high speed logic controller that implements thermometer-type control logic by utilizing scan flip-flops and a gated clockNAT SEMICONDUCTOR CORP·Filed 2004·Granted Sep 19, 2006·3 cites·22 claims
- 3040US2009177424A13-Dimensional method for determining the clock-to-Q delay of a flipflopPASQUALINI RONALD·Filed 2008·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →