Inventor · disambiguated record
Robert Pawlowski
Also filed as: PAWLOWSKI ROBERT · PAWLOWSKI ROBERT S
15 granted patents·18 pending applications·20 citations·filing 2017–2024
87Inventor score
Top patents by PatentIndex Score
33 records- 0187US10929132B1Systems and methods for ISA support for indirect loads and stores for efficiently accessing compressed lists in graph applicationsINTEL CORP·Filed 2019·Granted Feb 23, 2021·8 cites·20 claims
- 0285US10795819B1Multi-processor system with configurable cache sub-domains and cross-die memory coherencyINTEL CORP·Filed 2019·Granted Oct 6, 2020·4 cites·20 claims
- 0381US10476492B2Structures and operations of integrated circuits having network of configurable switchesINTEL CORP·Filed 2018·Granted Nov 12, 2019·4 cites·25 claims
- 0478US12455738B2Large-scale matrix restructuring and matrix-scalar operationsINTEL CORP·Filed 2020·Granted Oct 28, 2025·1 cites·15 claims
- 0573US11061742B2System, apparatus and method for barrier synchronization in a multi-threaded processorINTEL CORP·Filed 2018·Granted Jul 13, 2021·2 cites·18 claims
- 0664US10983793B2Array broadcast and reduction systems and methodsINTEL CORP·Filed 2019·Granted Apr 20, 2021·1 cites·26 claims
- 0759US11630691B2Memory system architecture for multi-threaded processorsINTEL CORP·Filed 2021·Granted Apr 18, 2023·0 cites·24 claims
- 0858US12360824B2Return value storage for atomic functionsINTEL CORP·Filed 2021·Granted Jul 15, 2025·0 cites·20 claims
- 0958US11960922B2System, apparatus and method for user space object coherency in a processorINTEL CORP·Filed 2020·Granted Apr 16, 2024·0 cites·16 claims
- 1054US12388712B2In-network multicast operationsINTEL CORP·Filed 2021·Granted Aug 12, 2025·0 cites·26 claims
- 1154US12153932B2Techniques for acceleration of a prefix-scan operationINTEL CORP·Filed 2020·Granted Nov 26, 2024·0 cites·25 claims
- 1254US11106494B2Memory system architecture for multi-threaded processorsINTEL CORP·Filed 2018·Granted Aug 31, 2021·0 cites·23 claims
- 1353US2022222075A1Instruction set architecture with programmable direct memory access and expanded fence/flush operationsPAWLOWSKI ROBERT S·Filed 2022·Application pending·0 cites
- 1453US2024119015A1Instruction set architecture support for at-speed near-memory atomic operations in a non-cached distributed memory systemINTEL CORP·Filed 2023·Application pending·0 cites
- 1553US2024241645A1Instruction set architecture and hardware support for hash operationsINTEL CORP·Filed 2024·Application pending·0 cites
- 1653US2025173149A1Apparatus and method for reconciling conflicting cacheline modificationsINTEL CORP·Filed 2023·Application pending·0 cites
- 1752US2024160580A1Virtual extension to global address space and system securityINTEL CORP·Filed 2023·Application pending·0 cites
- 1852US2024028555A1Multi-dimensional network sorted array intersectionPAWLOWSKI ROBERT·Filed 2023·Application pending·0 cites
- 1951US12158852B2Circuitry and methods for direct memory access instruction set architecture support for flexible dense compute using a reconfigurable spatial arrayINTEL CORP·Filed 2021·Granted Dec 3, 2024·0 cites·24 claims
- 2051US2025200163A1Apparatus and method for per-user secure access control with fine granularityINTEL CORP·Filed 2023·Application pending·0 cites
- 2150US12204901B2Cache support for indirect loads and indirect stores in graph applicationsINTEL CORP·Filed 2021·Granted Jan 21, 2025·0 cites·20 claims
- 2250US2025110918A1Offloading function streamsINTEL CORP·Filed 2023·Application pending·0 cites
- 2350US2024020253A1Instruction set architecture support for data type conversion in near-memory dma operationsINTEL CORP·Filed 2023·Application pending·0 cites
- 2450US2025199962A1Apparatus and method for remote virtual to physical address translationsINTEL CORP·Filed 2023·Application pending·0 cites
- 2550US2024045829A1Multi-dimensional network sorted array mergingINTEL CORP·Filed 2023·Application pending·0 cites
- 2649US11360809B2Multithreaded processor core with hardware-assisted task schedulingINTEL CORP·Filed 2018·Granted Jun 14, 2022·0 cites·18 claims
- 2749US2023315451A1Technology to support bitmap manipulation operations using a direct memory access instruction set architectureINTEL CORP·Filed 2023·Application pending·0 cites
- 2849US2024069921A1Dynamically reconfigurable processing coreINTEL CORP·Filed 2023·Application pending·0 cites
- 2948US2023333998A1Instruction set architecture support for conditional direct memory access data movement operationsINTEL CORP·Filed 2023·Application pending·0 cites
- 3042US2020401412A1Hardware support for dual-memory atomic operationsINTEL CORP·Filed 2019·Application pending·0 cites
- 3140US2024256283A1Computing architectureINTEL CORP·Filed 2022·Application pending·0 cites
- 3237US2019303159A1Instruction set architecture to facilitate energy-efficient computing for exascale architecturesINTEL CORP·Filed 2018·Application pending·0 cites
- 3337US2018285252A1Optimized memory access bandwidth devices, systems, and methods for processing low spatial locality dataINTEL CORP·Filed 2017·Application pending·0 cites
Join the waitlist — get patent alerts
Get an alert when Robert Pawlowski files or is granted a new patent.
We store only your email — no account needed. See our privacy policy.
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →