Inventor · disambiguated record
Ronny Ronen
Also filed as: RONEN RONNY
86 granted patents·9 pending applications·2,240 citations·filing 1995–2020
99Inventor score
Top patents by PatentIndex Score
95 records- 0198US6804632B2Distribution of processing activity across processing hardware based on power consumption considerationsINTEL CORP·Filed 2001·Granted Oct 12, 2004·261 cites·37 claims
- 0296US7437581B2Method and apparatus for varying energy per instruction according to the amount of available parallelismINTEL CORP·Filed 2004·Granted Oct 14, 2008·138 cites·50 claims
- 0396US7043405B2Distribution of processing activity in a multiple core microprocessorINTEL CORP·Filed 2004·Granted May 9, 2006·110 cites·48 claims
- 0495US6687838B2Low-power processor hint, such as from a PAUSE instructionINTEL CORP·Filed 2000·Granted Feb 3, 2004·105 cites·46 claims
- 0591US7464278B2Combining power prediction and optimal control approaches for performance optimization in thermally limited designsINTEL CORP·Filed 2005·Granted Dec 9, 2008·30 cites·22 claims
- 0689US8245070B2Method for optimizing voltage-frequency setup in multi-core processor systemsFINKELSTEIN LEV·Filed 2008·Granted Aug 14, 2012·23 cites·15 claims
- 0789US6675376B2System and method for fusing instructionsINTEL CORP·Filed 2000·Granted Jan 6, 2004·52 cites·26 claims
- 0889US6549987B1Cache structure for storing variable length dataINTEL CORP·Filed 2000·Granted Apr 15, 2003·49 cites·18 claims
- 0988US9720730B2Providing an asymmetric multicore processor system transparently to an operating systemGINZBURG BORIS·Filed 2011·Granted Aug 1, 2017·15 cites·20 claims
- 1088US9396020B2Context switching mechanism for a processing core having a general purpose CPU core and a tightly coupled acceleratorGINZBURG BORIS·Filed 2012·Granted Jul 19, 2016·10 cites·11 claims
- 1188US8402290B2Power management for multiple processor coresFINKELSTEIN LEV·Filed 2008·Granted Mar 19, 2013·17 cites·30 claims
- 1288US7757065B1Instruction segment recording schemeINTEL CORP·Filed 2000·Granted Jul 13, 2010·55 cites·19 claims
- 1387US10078519B2Apparatus and method for accelerating operations in a processor which uses shared virtual memoryINTEL CORP·Filed 2016·Granted Sep 18, 2018·4 cites·3 claims
- 1486US10120691B2Context switching mechanism for a processor having a general purpose core and a tightly coupled acceleratorINTEL CORP·Filed 2016·Granted Nov 6, 2018·4 cites·20 claims
- 1585US7096145B2Deterministic power-estimation for thermal controlINTEL CORP·Filed 2002·Granted Aug 22, 2006·39 cites·19 claims
- 1685US6601161B2Method and system for branch target prediction using path informationINTEL CORP·Filed 1998·Granted Jul 29, 2003·105 cites·24 claims
- 1783US9405701B2Apparatus and method for accelerating operations in a processor which uses shared virtual memoryWEISSMANN ELIEZER·Filed 2012·Granted Aug 2, 2016·6 cites·22 claims
- 1883US6950903B2Power reduction for processor front-end by caching decoded instructionsINTEL CORP·Filed 2001·Granted Sep 27, 2005·29 cites·12 claims
- 1983US6134643AMethod and apparatus for cache line prediction and prefetching using a prefetch controller and buffer and access historyINTEL CORP·Filed 1997·Granted Oct 17, 2000·111 cites·29 claims
- 2082US7171543B1Method and apparatus for executing a 32-bit application by confining the application to a 32-bit address space subset in a 64-bit processorINTEL CORP·Filed 2000·Granted Jan 30, 2007·35 cites·20 claims
- 2182US6505293B1Register renaming to optimize identical register valuesINTEL CORP·Filed 1999·Granted Jan 7, 2003·98 cites·11 claims
- 2282US6438673B1Correlated address predictionINTEL CORP·Filed 1999·Granted Aug 20, 2002·99 cites·18 claims
- 2381US10185566B2Migrating tasks between asymmetric computing elements of a multi-core processorNAVEH ALON·Filed 2012·Granted Jan 22, 2019·5 cites·19 claims
- 2481US9164923B2Dynamic pinning of virtual pages shared between different type processors of a heterogeneous computing platformSHEAFFER GAD·Filed 2011·Granted Oct 20, 2015·5 cites·22 claims
- 2581US7586281B2Methods and apparatus for optimal voltage and frequency control of thermally limited systemsINTEL CORP·Filed 2006·Granted Sep 8, 2009·10 cites·3 claims
- 2681US6631445B2Cache structure for storing variable length dataINTEL CORP·Filed 2003·Granted Oct 7, 2003·26 cites·19 claims
- 2780US6857060B2System, apparatus and method for prioritizing instructions and eliminating useless instructionsINTEL CORP·Filed 2001·Granted Feb 15, 2005·29 cites·25 claims
- 2880US6697932B1System and method for early resolution of low confidence branches and safe data cache accessesINTEL CORP·Filed 1999·Granted Feb 24, 2004·92 cites·26 claims
- 2979US7130966B2Power reduction for processor front-end by caching decoded instructionsINTEL CORP·Filed 2005·Granted Oct 31, 2006·7 cites·9 claims
- 3078US10558490B2Mechanism for issuing requests to an accelerator from multiple threadsRONEN RONNY·Filed 2012·Granted Feb 11, 2020·4 cites·19 claims
- 3178US9152572B2Translation lookaside buffer for multiple context compute engineRONEN RONNY·Filed 2011·Granted Oct 6, 2015·5 cites·16 claims
- 3277US7062638B2Prediction of issued silent store operations for allowing subsequently issued loads to bypass unexecuted silent stores and confirming the bypass upon execution of the storesINTEL CORP·Filed 2000·Granted Jun 13, 2006·25 cites·26 claims
- 3375US7689804B2Selectively protecting a register fileINTEL CORP·Filed 2006·Granted Mar 30, 2010·7 cites·22 claims
- 3475US6625723B1Unified renaming scheme for load and store instructionsINTEL CORP·Filed 1999·Granted Sep 23, 2003·68 cites·16 claims
- 3574US11243768B2Mechanism for saving and retrieving micro-architecture contextINTEL CORP·Filed 2019·Granted Feb 8, 2022·1 cites·21 claims
- 3674US5987595AMethod and apparatus for predicting when load instructions can be executed out-of orderINTEL CORP·Filed 1997·Granted Nov 16, 1999·68 cites·28 claims
- 3773US7458069B2System and method for fusing instructionsINTEL CORP·Filed 2004·Granted Nov 25, 2008·15 cites·28 claims
- 3873US7141953B2Methods and apparatus for optimal voltage and frequency control of thermally limited systemsINTEL CORP·Filed 2004·Granted Nov 28, 2006·20 cites·30 claims
- 3973US7017026B2Generating lookahead tracked register value based on arithmetic operation indicationINTEL CORP·Filed 2004·Granted Mar 21, 2006·15 cites·20 claims
- 4073US6594754B1Mapping destination logical register to physical register storing immediate or renamed source register of move instruction and using mapping countersINTEL CORP·Filed 1999·Granted Jul 15, 2003·63 cites·24 claims
- 4172US6647482B1Method for optimized representation of page table entriesINTEL CORP·Filed 2000·Granted Nov 11, 2003·16 cites·6 claims
- 4271US5790822AMethod and apparatus for providing a re-ordered instruction cache in a pipelined microprocessorINTEL CORP·Filed 1996·Granted Aug 4, 1998·58 cites·29 claims
- 4369US7934110B2Dynamically managing thermal levels in a processing systemINTEL CORP·Filed 2007·Granted Apr 26, 2011·4 cites·20 claims
- 4469US6678816B2Method for optimized representation of page table entriesINTEL CORP·Filed 2003·Granted Jan 13, 2004·12 cites·13 claims
- 4568US11275637B2Aggregated page fault signaling and handlingINTEL CORP·Filed 2020·Granted Mar 15, 2022·0 cites·25 claims
- 4667US9348594B2Core switching acceleration in asymmetric multiprocessor systemYAMADA KOICHI·Filed 2011·Granted May 24, 2016·2 cites·19 claims
- 4766US9891980B2Aggregated page fault signaling and handlineGINZBURG BORIS·Filed 2011·Granted Feb 13, 2018·1 cites·27 claims
- 4866US7155599B2Method and apparatus for a register renaming structureINTEL CORP·Filed 2000·Granted Dec 26, 2006·11 cites·15 claims
- 4965US8572358B2Meta predictor restoration upon detecting mispredictionRONEN RONNY·Filed 2012·Granted Oct 29, 2013·1 cites·20 claims
- 5065US7802076B2Method and apparatus to vectorize multiple input instructionsINTEL CORP·Filed 2004·Granted Sep 21, 2010·12 cites·17 claims
Showing the top 50 of 95 patent records by PatentIndex Score.
Join the waitlist — get patent alerts
Get an alert when Ronny Ronen files or is granted a new patent.
We store only your email — no account needed. See our privacy policy.
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →