Inventor · disambiguated record
Robert M. Salter, Iii
Also filed as: SALTER III ROBERT M
19 granted patents·1 pending application·656 citations·filing 1992–2023
96Inventor score
Top patents by PatentIndex Score
20 records- 0197US7430137B2Non-volatile memory cells in a field programmable gate arrayACTEL CORP·Filed 2007·Granted Sep 30, 2008·47 cites·7 claims
- 0296US5606710AMultiple chip package processor having feed through paths on one dieNAT SEMICONDUCTOR CORP·Filed 1994·Granted Feb 25, 1997·131 cites·13 claims
- 0394US7301821B1Volatile data storage in a non-volatile memory cell arrayACTEL CORP·Filed 2005·Granted Nov 27, 2007·26 cites·27 claims
- 0494US5566344AIn-system programming architecture for a multiple chip processorNAT SEMICONDUCTOR CORP·Filed 1995·Granted Oct 15, 1996·93 cites·10 claims
- 0593US7362610B1Programming method for non-volatile memory and non-volatile memory-based programmable logic deviceACTEL CORP·Filed 2005·Granted Apr 22, 2008·30 cites·17 claims
- 0688US5623686ANon-volatile memory control and data loading architecture for multiple chip processorNAT SEMICONDUCTOR CORP·Filed 1995·Granted Apr 22, 1997·85 cites·9 claims
- 0784US5581779AMultiple chip processor architecture with memory interface control register for in-system programmingNAT SEMICONDUCTOR CORP·Filed 1995·Granted Dec 3, 1996·83 cites·13 claims
- 0879US6252273B1Nonvolatile reprogrammable interconnect cell with FN tunneling device for programming and eraseACTEL CORP·Filed 1998·Granted Jun 26, 2001·45 cites·17 claims
- 0975US5838040ANonvolatile reprogrammable interconnect cell with FN tunneling in senseGATEFIELD CORP·Filed 1997·Granted Nov 17, 1998·39 cites·8 claims
- 1067US7623390B2Programming method for non-volatile memory and non-volatile memory-based programmable logic deviceACTEL CORP·Filed 2008·Granted Nov 24, 2009·5 cites·17 claims
- 1159US5773862AFloating gate FGPA cell with separated select deviceZYCAD CORP·Filed 1996·Granted Jun 30, 1998·19 cites·10 claims
- 1256US2023390557A1Electrical stimulation device for applying frequency and peak voltage having inverse relationshipNUENERCHI INC·Filed 2023·Application pending·0 cites
- 1354US6072720ANonvolatile reprogrammable interconnect cell with programmable buried bitlineGATEFIELD CORP·Filed 1998·Granted Jun 6, 2000·16 cites·29 claims
- 1452US6137728ANonvolatile reprogrammable interconnect cell with programmable buried source/drain in sense transistorGATEFIELD CORP·Filed 1998·Granted Oct 24, 2000·14 cites·8 claims
- 1552US5359555AColumn selector circuit for shared column CMOS EPROMNAT SEMICONDUCTOR CORP·Filed 1992·Granted Oct 25, 1994·15 cites·4 claims
- 1650US5598573AMultiple chip processor architecture with reset intercept circuitNAT SEMICONDUCTOR CORP·Filed 1995·Granted Jan 28, 1997·8 cites·3 claims
- 1744US7573746B1Volatile data storage in a non-volatile memory cell arrayACTEL CORP·Filed 2007·Granted Aug 11, 2009·0 cites·19 claims
- 1843US7593268B2Method for erasing programmable interconnect cells for field programmable gate arrays using reverse bias voltageACTEL CORP·Filed 2006·Granted Sep 22, 2009·0 cites·6 claims
- 1942US11738195B2Electrical stimulation device for applying frequency and peak voltage having inverse relationshipNUENERCHI INC·Filed 2019·Granted Aug 29, 2023·0 cites·21 claims
- 2040US8803548B2Apparatus and methods for a tamper resistant bus for secure lock bit transferSALTER III ROBERT M·Filed 2012·Granted Aug 12, 2014·0 cites·4 claims
Join the waitlist — get patent alerts
Get an alert when Robert M. Salter, Iii files or is granted a new patent.
We store only your email — no account needed. See our privacy policy.
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →