Inventor · disambiguated record
Rolf Sautter
Also filed as: SAUTTER ROLF
45 granted patents·5 pending applications·171 citations·filing 2000–2024
97Inventor score
Top patents by PatentIndex Score
50 records- 0188US7813163B2Single-ended read and differential write schemeIBM·Filed 2008·Granted Oct 12, 2010·20 cites·11 claims
- 0287US9431098B1Structure for reducing pre-charge voltage for static random-access memory arraysIBM·Filed 2015·Granted Aug 30, 2016·4 cites·10 claims
- 0387US9431096B1Hierarchical negative bitline boost write assist for SRAM memory devicesIBM·Filed 2015·Granted Aug 30, 2016·10 cites·13 claims
- 0485US10002661B2Structure for reducing pre-charge voltage for static random-access memory arraysIBM·Filed 2017·Granted Jun 19, 2018·3 cites·20 claims
- 0583US6785781B2Read/write alignment scheme for port reduction of multi-port SRAM cellsIBM·Filed 2001·Granted Aug 31, 2004·36 cites·13 claims
- 0682US10831970B2Layout of a memory cell of an integrated circuitIBM·Filed 2019·Granted Nov 10, 2020·4 cites·20 claims
- 0780US10833089B2Buried conductive layer supplying digital circuitsIBM·Filed 2018·Granted Nov 10, 2020·3 cites·18 claims
- 0880US6990038B1Clock driver and boundary latch for a multi-port SRAMIBM·Filed 2005·Granted Jan 24, 2006·13 cites·28 claims
- 0975US11164879B2Microelectronic device with a memory element utilizing stacked vertical devicesIBM·Filed 2018·Granted Nov 2, 2021·2 cites·23 claims
- 1072US7936638B2Enhanced programmable pulsewidth modulating circuit for array clock generationIBM·Filed 2009·Granted May 3, 2011·6 cites·19 claims
- 1171US10593420B2Testing content addressable memory and random access memoryIBM·Filed 2018·Granted Mar 17, 2020·2 cites·11 claims
- 1270US10170199B2Testing content addressable memory and random access memoryIBM·Filed 2018·Granted Jan 1, 2019·2 cites·1 claims
- 1370US7936198B2Progamable control clock circuit for arraysIBM·Filed 2008·Granted May 3, 2011·4 cites·16 claims
- 1469US10079070B2Testing content addressable memory and random access memoryIBM·Filed 2016·Granted Sep 18, 2018·2 cites·9 claims
- 1568US8422313B2Reduced power consumption memory circuitryBUETTNER STEFAN·Filed 2011·Granted Apr 16, 2013·4 cites·20 claims
- 1667US9098659B2Advanced array local clock buffer base block circuitIBM·Filed 2014·Granted Aug 4, 2015·2 cites·7 claims
- 1764US8659963B2Enhanced power savings for memory arraysDENGLER OSAMA·Filed 2012·Granted Feb 25, 2014·4 cites·18 claims
- 1862US9401698B1Transforming a phase-locked-loop generated chip clock signal to a local clock signalIBM·Filed 2015·Granted Jul 26, 2016·1 cites·17 claims
- 1960US11881853B2True complement dynamic circuit and method for combining binary dataIBM·Filed 2022·Granted Jan 23, 2024·0 cites·24 claims
- 2058US6681313B1Method and system for fast access to a translation lookaside bufferIBM·Filed 2000·Granted Jan 20, 2004·9 cites·10 claims
- 2157US7755394B2Circuit combining level shift function with gated resetIBM·Filed 2008·Granted Jul 13, 2010·3 cites·1 claims
- 2255US10553282B2Content addressable memory cell and arrayIBM·Filed 2015·Granted Feb 4, 2020·2 cites·19 claims
- 2355US9727680B2Structure for reducing pre-charge voltage for static random-access memory arraysIBM·Filed 2016·Granted Aug 8, 2017·0 cites·18 claims
- 2455US9721049B2Structure for reducing pre-charge voltage for static random-access memory arraysIBM·Filed 2016·Granted Aug 1, 2017·0 cites·10 claims
- 2555US9721050B2Structure for reducing pre-charge voltage for static random-access memory arraysIBM·Filed 2016·Granted Aug 1, 2017·0 cites·14 claims
- 2655US9536608B1Content addressable memory deviceIBM·Filed 2015·Granted Jan 3, 2017·1 cites·20 claims
- 2754US7295481B2Power saving by disabling cyclic bitline prechargeIBM·Filed 2004·Granted Nov 13, 2007·9 cites·5 claims
- 2854US7095252B2Charge sharing reduction by applying intrinsic parallelism in complex dynamic domino type CMOS gatesIBM·Filed 2004·Granted Aug 22, 2006·7 cites·8 claims
- 2953US6918119B2Method and system to improve usage of an instruction window buffer in multi-processor, parallel processing environmentsIBM·Filed 2001·Granted Jul 12, 2005·3 cites·16 claims
- 3052US8237481B2Low power programmable clock delay generator with integrated decode functionCHAN YUEN H·Filed 2008·Granted Aug 7, 2012·2 cites·5 claims
- 3151US11328110B2Integrated circuit including logic circuitryIBM·Filed 2020·Granted May 10, 2022·0 cites·15 claims
- 3251US6496398B2Content addressable memoryIBM·Filed 2001·Granted Dec 17, 2002·8 cites·11 claims
- 3349US10804266B2Microelectronic device utilizing stacked vertical devicesIBM·Filed 2018·Granted Oct 13, 2020·0 cites·24 claims
- 3449US7406495B2Adder structure with midcycle latch for power reductionIBM·Filed 2004·Granted Jul 29, 2008·1 cites·3 claims
- 3545US7650535B2Array delete mechanisms for shipping a microprocessor with defective arraysIBM·Filed 2006·Granted Jan 19, 2010·0 cites·20 claims
- 3645US7224190B2Midcycle latch for power saving and switching reductionIBM·Filed 2004·Granted May 29, 2007·4 cites·6 claims
- 3745US2025118360A1Memory device, assist cell and double assist cell for a memory deviceIBM·Filed 2024·Application pending·0 cites
- 3843US9537474B2Transforming a phase-locked-loop generated chip clock signal to a local clock signalIBM·Filed 2015·Granted Jan 3, 2017·0 cites·8 claims
- 3943US2013091375A1Advanced Array Local Clock Buffer Base Block CircuitDENGLER OSAMA·Filed 2011·Application pending·0 cites
- 4042US6629215B2Multiple port memory apparatusIBM·Filed 2001·Granted Sep 30, 2003·0 cites·19 claims
- 4140US11171142B2Integrated circuit with vertical structures on nodes of a gridIBM·Filed 2018·Granted Nov 9, 2021·0 cites·24 claims
- 4240US9767872B2Current-mode sense amplifier and reference current circuitryIBM·Filed 2016·Granted Sep 19, 2017·0 cites·15 claims
- 4339US9564188B2Current-mode sense amplifier and reference current circuitryIBM·Filed 2015·Granted Feb 7, 2017·0 cites·15 claims
- 4438US8942052B2Complementary metal-oxide-semiconductor (CMOS) min/max voltage circuit for switching between multiple voltagesIBM·Filed 2012·Granted Jan 27, 2015·0 cites·24 claims
- 4535US2008258769A1Tri-State Circuit Element Plus Tri-State-Multiplexer CircuitryIBM·Filed 2008·Application pending·0 cites
- 4634US9666278B2Content addressable memory array comprising geometric footprint and RAM cell block located between two parts of a CAM cell blockIBM·Filed 2015·Granted May 30, 2017·0 cites·20 claims
- 4734US8086657B2Adder structure with midcycle latch for power reductionHALLER WILHELM·Filed 2008·Granted Dec 27, 2011·0 cites·7 claims
- 4833US2008298137A1Method and structure for domino read bit line and set reset latchCHAN YUEN HUNG·Filed 2008·Application pending·0 cites
- 4931US2013128684A1Reduced leakage banked wordline headerBUETTNER STEFAN·Filed 2012·Application pending·0 cites
- 5028US9484073B1Current-mode sense amplifierIBM·Filed 2015·Granted Nov 1, 2016·0 cites·17 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →