Inventor · disambiguated record
Ronak Singhal
Also filed as: SINGHAL RONAK
38 granted patents·6 pending applications·326 citations·filing 2000–2025
97Inventor score
Top patents by PatentIndex Score
44 records- 0196US9858167B2Monitoring the operation of a processorINTEL CORP·Filed 2015·Granted Jan 2, 2018·16 cites·5 claims
- 0295US9786338B2Multiple register memory access instructions, processors, methods, and systemsINTEL CORP·Filed 2016·Granted Oct 10, 2017·9 cites·20 claims
- 0393US6981129B1Breaking replay dependency loops in a processor using a rescheduled replay queueINTEL CORP·Filed 2000·Granted Dec 27, 2005·87 cites·23 claims
- 0492US11442734B2Packed data element predication processors, methods, systems, and instructionsINTEL CORP·Filed 2021·Granted Sep 13, 2022·2 cites·26 claims
- 0592US10163468B2Multiple register memory access instructions, processors, methods, and systemsINTEL CORP·Filed 2017·Granted Dec 25, 2018·5 cites·20 claims
- 0690US9424034B2Multiple register memory access instructions, processors, methods, and systemsINTEL CORP·Filed 2013·Granted Aug 23, 2016·8 cites·29 claims
- 0790US6877086B1Method and apparatus for rescheduling multiple micro-operations in a processor using a replay queue and a counterINTEL CORP·Filed 2000·Granted Apr 5, 2005·66 cites·19 claims
- 0889US10430193B2Packed data element predication processors, methods, systems, and instructionsINTEL CORP·Filed 2018·Granted Oct 1, 2019·4 cites·22 claims
- 0988US7181598B2Prediction of load-store dependencies in a processing agentINTEL CORP·Filed 2002·Granted Feb 20, 2007·52 cites·18 claims
- 1087US10170165B2Multiple register memory access instructions, processors, methods, and systemsINTEL CORP·Filed 2017·Granted Jan 1, 2019·4 cites·20 claims
- 1187US10141033B2Multiple register memory access instructions, processors, methods, and systemsINTEL CORP·Filed 2017·Granted Nov 27, 2018·4 cites·20 claims
- 1287US10102888B2Multiple register memory access instructions, processors, methods, and systemsINTEL CORP·Filed 2017·Granted Oct 16, 2018·4 cites·32 claims
- 1386US10153011B2Multiple register memory access instructions, processors, methods, and systemsINTEL CORP·Filed 2017·Granted Dec 11, 2018·4 cites·20 claims
- 1486US9990202B2Packed data element predication processors, methods, systems, and instructionsINTEL CORP·Filed 2013·Granted Jun 5, 2018·6 cites·26 claims
- 1584US10963257B2Packed data element predication processors, methods, systems, and instructionsINTEL CORP·Filed 2019·Granted Mar 30, 2021·2 cites·16 claims
- 1684US7757045B2Synchronizing recency information in an inclusive cache hierarchyINTEL CORP·Filed 2006·Granted Jul 13, 2010·14 cites·23 claims
- 1783US10153012B2Multiple register memory access instructions, processors, methods, and systemsINTEL CORP·Filed 2017·Granted Dec 11, 2018·3 cites·18 claims
- 1883US9563564B2Cache allocation with code and data prioritizationINTEL CORP·Filed 2015·Granted Feb 7, 2017·3 cites·20 claims
- 1982US11294809B2Apparatuses and methods for a processor architectureINTEL CORP·Filed 2018·Granted Apr 5, 2022·2 cites·7 claims
- 2082US10496413B2Efficient hardware-based extraction of program instructions for critical pathsINTEL CORP·Filed 2017·Granted Dec 3, 2019·4 cites·22 claims
- 2180US10089229B2Cache allocation with code and data prioritizationINTEL CORP·Filed 2017·Granted Oct 2, 2018·2 cites·20 claims
- 2276US12039336B2Packed data element predication processors, methods, systems, and instructionsINTEL CORP·Filed 2022·Granted Jul 16, 2024·0 cites·21 claims
- 2376US10579414B2Misprediction-triggered local history-based branch predictionINTEL CORP·Filed 2017·Granted Mar 3, 2020·2 cites·18 claims
- 2473US12130740B2Apparatuses and methods for a processor architectureINTEL CORP·Filed 2022·Granted Oct 29, 2024·0 cites·15 claims
- 2572US2025217882A1Systems, Apparatuses, and Methods for Resource Bandwidth EnforcementINTEL CORP·Filed 2025·Application pending·0 cites
- 2670US12198186B2Systems, apparatuses, and methods for resource bandwidth enforcementINTEL CORP·Filed 2021·Granted Jan 14, 2025·0 cites·13 claims
- 2769US10719355B2Criticality based port schedulingINTEL CORP·Filed 2018·Granted Jul 21, 2020·1 cites·20 claims
- 2868US9081688B2Obtaining data for redundant multithreading (RMT) executionHINTON GLENN J·Filed 2008·Granted Jul 14, 2015·4 cites·15 claims
- 2966US11048588B2Monitoring the operation of a processorINTEL CORP·Filed 2020·Granted Jun 29, 2021·0 cites·8 claims
- 3065US7383418B2Method and apparatus for prefetching data to a lower level cache memoryINTEL CORP·Filed 2004·Granted Jun 3, 2008·12 cites·2 claims
- 3163US9092214B2SIMD processor with programmable counters externally configured to count executed instructions having operands of particular register size and element size combinationKNAUTH LAURA A·Filed 2012·Granted Jul 28, 2015·2 cites·14 claims
- 3261US8793689B2Redundant multithreading processorHINTON GLENN J·Filed 2010·Granted Jul 29, 2014·1 cites·23 claims
- 3360US10599547B2Monitoring the operation of a processorINTEL CORP·Filed 2017·Granted Mar 24, 2020·0 cites·13 claims
- 3460US9594648B2Controlling non-redundant execution in a redundant multithreading (RMT) processorHINTON GLENN J·Filed 2008·Granted Mar 14, 2017·2 cites·12 claims
- 3559US7457938B2Staggered execution stack for vector processingINTEL CORP·Filed 2005·Granted Nov 25, 2008·1 cites·24 claims
- 3658US12417182B2De-prioritizing speculative code lines in on-chip cachesINTEL CORP·Filed 2021·Granted Sep 16, 2025·0 cites·21 claims
- 3750US10228941B2Processors, methods, and systems to access a set of registers as either a plurality of smaller registers or a combined larger registerINTEL CORP·Filed 2013·Granted Mar 12, 2019·0 cites·30 claims
- 3850US9558127B2Instruction and logic for a cache prefetcher and dataless fill bufferINTEL CORP·Filed 2014·Granted Jan 31, 2017·0 cites·17 claims
- 3949US7457932B2Load mechanismINTEL CORP·Filed 2005·Granted Nov 25, 2008·0 cites·25 claims
- 4048US2016026464A1Programmable Counters for Counting Floating-Point Operations in SIMD ProcessorsINTEL CORP·Filed 2015·Application pending·0 cites
- 4145US2005138290A1System and method for instruction reschedulingINTEL CORP·Filed 2003·Application pending·0 cites
- 4244US2015186140A1Opcode trappingTOLL BRET L·Filed 2013·Application pending·0 cites
- 4340US2018349144A1Method and apparatus for branch prediction utilizing primary and secondary branch predictorsINTEL CORP·Filed 2017·Application pending·0 cites
- 4437US2011296096A1Method And Apparatus For Virtualized Microcode SequencingZOU XIANG·Filed 2010·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →