Inventor · disambiguated record
Rodney Wayne Smith
Also filed as: SMITH RODNEY · SMITH RODNEY W · SMITH RODNEY WAYNE
71 granted patents·20 pending applications·446 citations·filing 1976–2022
99Inventor score
Files withQUALCOMM INC54MICROSOFT TECHNOLOGY LICENSING LLC13SMITH RODNEY W7IBM6STEMPEL BRIAN MICHAEL3
Top patents by PatentIndex Score
91 records- 0196US10108417B2Storing narrow produced values for instruction operands directly in a register map in an out-of-order processorQUALCOMM INC·Filed 2015·Granted Oct 23, 2018·42 cites·30 claims
- 0296US7716460B2Effective use of a BHT in processor having variable length instruction set execution modesQUALCOMM INC·Filed 2006·Granted May 11, 2010·51 cites·16 claims
- 0395US11061677B1Recovering register mapping state of a flushed instruction employing a snapshot of another register mapping state and traversing reorder buffer (ROB) entries in a processorMICROSOFT TECHNOLOGY LICENSING LLC·Filed 2020·Granted Jul 13, 2021·9 cites·40 claims
- 0490US8438372B2Link stack repair of erroneous speculative updateDIEFFENDERFER JAMES NORRIS·Filed 2011·Granted May 7, 2013·15 cites·27 claims
- 0590US7624256B2System and method wherein conditional instructions unconditionally provide outputQUALCOMM INC·Filed 2005·Granted Nov 24, 2009·24 cites·15 claims
- 0687US7624254B2Segmented pipeline flushing for mispredicted branchesQUALCOMM INC·Filed 2007·Granted Nov 24, 2009·18 cites·1 claims
- 0787US7278012B2Method and apparatus for efficiently accessing first and second branch history tables to predict branch instructionsQUALCOMM INC·Filed 2005·Granted Oct 2, 2007·18 cites·22 claims
- 0886US7587580B2Power efficient instruction prefetch mechanismQUALCOMM INC·Filed 2005·Granted Sep 8, 2009·14 cites·11 claims
- 0985US11113068B1Performing flush recovery using parallel walks of sliced reorder buffers (SROBs)MICROSOFT TECHNOLOGY LICENSING LLC·Filed 2020·Granted Sep 7, 2021·2 cites·20 claims
- 1085US7676659B2System, method and software to preload instructions from a variable-length instruction set with proper pre-decodingQUALCOMM INC·Filed 2007·Granted Mar 9, 2010·14 cites·24 claims
- 1183US7971044B2Link stack repair of erroneous speculative updateQUALCOMM INC·Filed 2007·Granted Jun 28, 2011·11 cites·23 claims
- 1282US7711927B2System, method and software to preload instructions from an instruction set other than one currently executingQUALCOMM INC·Filed 2007·Granted May 4, 2010·10 cites·19 claims
- 1381US10877768B1Minimizing traversal of a processor reorder buffer (ROB) for register rename map table (RMT) state recovery for interrupted instruction recovery in a processorMICROSOFT TECHNOLOGY LICENSING LLC·Filed 2019·Granted Dec 29, 2020·3 cites·26 claims
- 1479US7805588B2Caching memory attribute indicators with cached memory data fieldQUALCOMM INC·Filed 2005·Granted Sep 28, 2010·9 cites·26 claims
- 1579US7421568B2Power saving methods and apparatus to selectively enable cache bits based on known processor stateQUALCOMM INC·Filed 2005·Granted Sep 2, 2008·9 cites·18 claims
- 1674US7478228B2Apparatus for generating return address predictions for implicit and explicit subroutine callsQUALCOMM INC·Filed 2006·Granted Jan 13, 2009·5 cites·13 claims
- 1774US7415638B2Pre-decode error handling via branch correctionQUALCOMM INC·Filed 2004·Granted Aug 19, 2008·17 cites·22 claims
- 1873US7984279B2System and method for using a working global history registerQUALCOMM INC·Filed 2006·Granted Jul 19, 2011·6 cites·18 claims
- 1973US7827392B2Sliding-window, block-based branch target address cacheQUALCOMM INC·Filed 2006·Granted Nov 2, 2010·6 cites·16 claims
- 2073US7769983B2Caching instructions for a multiple-state processorQUALCOMM INC·Filed 2005·Granted Aug 3, 2010·6 cites·23 claims
- 2172US8943300B2Method and apparatus for generating return address predictions for implicit and explicit subroutine calls using predecode informationSTEMPEL BRIAN MICHAEL·Filed 2008·Granted Jan 27, 2015·5 cites·17 claims
- 2272US7210024B2Conditional instruction execution via emissary instruction for condition evaluationQUALCOMM INC·Filed 2005·Granted Apr 24, 2007·5 cites·19 claims
- 2371US7802055B2Virtually-tagged instruction cache with physically-tagged behaviorQUALCOMM INC·Filed 2006·Granted Sep 21, 2010·5 cites·22 claims
- 2471US7669039B2Use of register renaming system for forwarding intermediate results between constituent instructions of an expanded instructionQUALCOMM INC·Filed 2007·Granted Feb 23, 2010·5 cites·19 claims
- 2571US7404042B2Handling cache miss in an instruction crossing a cache line boundaryQUALCOMM INC·Filed 2005·Granted Jul 22, 2008·5 cites·18 claims
- 2670US10956162B2Operand-based reach explicit dataflow processors, and related methods and computer-readable mediaMICROSOFT TECHNOLOGY LICENSING LLC·Filed 2019·Granted Mar 23, 2021·1 cites·30 claims
- 2770US9477476B2Fusing immediate value, write-based instructions in instruction processing circuits, and related processor systems, methods, and computer-readable mediaQUALCOMM INC·Filed 2012·Granted Oct 25, 2016·3 cites·25 claims
- 2870US7203826B2Method and apparatus for managing a return stackQUALCOMM INC·Filed 2005·Granted Apr 10, 2007·4 cites·25 claims
- 2969US7962725B2Pre-decoding variable length instructionsQUALCOMM INC·Filed 2006·Granted Jun 14, 2011·4 cites·18 claims
- 3069US7366877B2Speculative instruction issue in a simultaneously multithreaded processorIBM·Filed 2003·Granted Apr 29, 2008·12 cites·14 claims
- 3168US9851774B2Method and apparatus for dynamic clock and voltage scaling in a computer processor based on program phaseQUALCOMM INC·Filed 2016·Granted Dec 26, 2017·1 cites·29 claims
- 3268US8145883B2Preloading instructions from an instruction set other than a currently executing instruction setSARTORIUS THOMAS ANDREW·Filed 2010·Granted Mar 27, 2012·2 cites·27 claims
- 3366US7650466B2Method and apparatus for managing cache partitioning using a dynamic boundaryQUALCOMM INC·Filed 2005·Granted Jan 19, 2010·3 cites·24 claims
- 3466US6948053B2Efficiently calculating a branch target addressIBM·Filed 2002·Granted Sep 20, 2005·11 cites·41 claims
- 3565US11842196B2Obsoleting values stored in registers in a processor based on processing obsolescent register-encoded instructionsMICROSOFT TECHNOLOGY LICENSING LLC·Filed 2021·Granted Dec 12, 2023·0 cites·23 claims
- 3665US8352713B2Debug circuit comparing processor instruction set operating modeQUALCOMM INC·Filed 2006·Granted Jan 8, 2013·4 cites·35 claims
- 3765US8082428B2Methods and system for resolving simultaneous predicted branch instructionsSMITH RODNEY WAYNE·Filed 2009·Granted Dec 20, 2011·3 cites·14 claims
- 3863US8661229B2Power efficient instruction prefetch mechanismSARTORIUS THOMAS ANDREW·Filed 2009·Granted Feb 25, 2014·2 cites·20 claims
- 3963US6816962B2Re-encoding illegal OP codes into a single illegal OP code to accommodate the extra bits associated with pre-decoded instructionsIBM·Filed 2002·Granted Nov 9, 2004·9 cites·16 claims
- 4062US11188334B2Obsoleting values stored in registers in a processor based on processing obsolescent register-encoded instructionsMICROSOFT TECHNOLOGY LICENSING LLC·Filed 2019·Granted Nov 30, 2021·0 cites·17 claims
- 4162US7917731B2Method and apparatus for prefetching non-sequential instruction addressesQUALCOMM INC·Filed 2006·Granted Mar 29, 2011·2 cites·26 claims
- 4261US7406613B2Translation lookaside buffer (TLB) suppression for intra-page program counter relative or absolute address branch instructionsQUALCOMM INC·Filed 2004·Granted Jul 29, 2008·7 cites·22 claims
- 4360US9411590B2Method to improve speed of executing return branch instructions in a processorQUALCOMM INC·Filed 2013·Granted Aug 9, 2016·1 cites·5 claims
- 4460US9195466B2Fusing conditional write instructions having opposite conditions in instruction processing circuits, and related processor systems, methods, and computer-readable mediaQUALCOMM INC·Filed 2012·Granted Nov 24, 2015·1 cites·25 claims
- 4560US8898437B2Predecode repair cache for instructions that cross an instruction cache lineSMITH RODNEY WAYNE·Filed 2007·Granted Nov 25, 2014·3 cites·21 claims
- 4660US7617387B2Methods and system for resolving simultaneous predicted branch instructionsQUALCOMM INC·Filed 2006·Granted Nov 10, 2009·1 cites·16 claims
- 4759US7681022B2Efficient interrupt return address save mechanismQUALCOMM INC·Filed 2006·Granted Mar 16, 2010·1 cites·22 claims
- 4859US7568070B2Instruction cache having fixed number of variable length instructionsQUALCOMM INC·Filed 2005·Granted Jul 28, 2009·1 cites·20 claims
- 4959US7376815B2Methods and apparatus to insure correct predecodeQUALCOMM INC·Filed 2005·Granted May 20, 2008·1 cites·20 claims
- 5059US4003275AWrenchSMITH RODNEY W·Filed 1976·Granted Jan 18, 1977·16 cites·1 claims
Showing the top 50 of 91 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →