Inventor · disambiguated record
Romain Wacquez
Also filed as: WACQUEZ ROMAIN
24 granted patents·3 pending applications·57 citations·filing 2006–2023
92Inventor score
Files withCOMMISSARIAT ENERGIE ATOMIQUE13ST MICROELECTRONICS CROLLES 23ST MICROELECTRONICS INC2ST MICROELECTRONICS SA2WACQUEZ ROMAIN2
Top patents by PatentIndex Score
27 records- 0188US8954363B2Digital-to-analogue converter and neuromorphic circuit using such a converterCOMMISSARIAT ENERGIE ATOMIQUE·Filed 2012·Granted Feb 10, 2015·24 cites·9 claims
- 0287US9991892B2Electronic device having a physical unclonable function identifierCOMMISSARIAT ENERGIE ATOMIQUE·Filed 2017·Granted Jun 5, 2018·8 cites·12 claims
- 0382US9570340B2Method of etching a crystalline semiconductor material by ion implantation and then chemical etching based on hydrogen chlorideCOMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENE ALT·Filed 2013·Granted Feb 14, 2017·5 cites·17 claims
- 0479US8460978B2Method for manufacturing a transistor with parallel semiconductor nanofingersCORONEL PHILIPPE·Filed 2006·Granted Jun 11, 2013·10 cites·29 claims
- 0573US9230991B2Method to co-integrate oppositely strained semiconductor devices on a same substrateST MICROELECTRONICS INC·Filed 2014·Granted Jan 5, 2016·2 cites·13 claims
- 0670US9236478B2Method for manufacturing a fin MOS transistorST MICROELECTRONICS SA·Filed 2014·Granted Jan 12, 2016·2 cites·25 claims
- 0769US11264479B2Process for producing FET transistorsCOMMISSARIAT ENERGIE ATOMIQUE·Filed 2013·Granted Mar 1, 2022·2 cites·21 claims
- 0866US12198940B2Method for modifying the strain state of a block of a semiconducting materialCOMMISSARIAT ENERGIE ATOMIQUE·Filed 2020·Granted Jan 14, 2025·0 cites·13 claims
- 0965US9231062B2Method for treating the surface of a silicon substrateCOMMISSARIAT ENERGIE ATOMIQUE·Filed 2013·Granted Jan 5, 2016·1 cites·20 claims
- 1061US8987854B2Microelectronic device with isolation trenches extending under an active areaCOMMISSARIAT ENERGIE ATOMIQUE·Filed 2013·Granted Mar 24, 2015·1 cites·13 claims
- 1159US12456968B2Coherent sampling true random number generation in FD-SOI technologyCOMMISSARIAT ENERGIE ATOMIQUE·Filed 2023·Granted Oct 28, 2025·0 cites·15 claims
- 1257US10879083B2Method for modifying the strain state of a block of a semiconducting materialCOMMISSARIAT A LENERGIE ATOMIQUE ET AUX ENE ALT·Filed 2014·Granted Dec 29, 2020·0 cites·11 claims
- 1356US8110460B2Method for producing stacked and self-aligned components on a substrateWACQUEZ ROMAIN·Filed 2009·Granted Feb 7, 2012·2 cites·15 claims
- 1450US9673329B2Method for manufacturing a fin MOS transistorST MICROELECTRONICS SA·Filed 2015·Granted Jun 6, 2017·0 cites·12 claims
- 1550US9460971B2Method to co-integrate oppositely strained semiconductor devices on a same substrateST MICROELECTRONICS INC·Filed 2015·Granted Oct 4, 2016·0 cites·37 claims
- 1649US2024201954A1Entropy source with embedded computing method for true random number generationCOMMISSARIAT ENERGIE ATOMIQUE·Filed 2023·Application pending·0 cites
- 1747US8877618B2Method for producing a field effect transistor with a SiGe channel by ion implantationCOMMISSARIAT ENERGIE ATOMIQUE·Filed 2013·Granted Nov 4, 2014·0 cites·7 claims
- 1845US7803668B2Transistor and fabrication processST MICROELECTRONICS CROLLES 2·Filed 2007·Granted Sep 28, 2010·0 cites·17 claims
- 1942US9396984B2Method of producing a microelectronic device in a monocrystalline semiconductor substrate with isolation trenches partially formed under an active regionVINET MAUD·Filed 2012·Granted Jul 19, 2016·0 cites·12 claims
- 2042US7994008B2Transistor device with two planar gates and fabrication processST MICROELECTRONICS CROLLES 2·Filed 2007·Granted Aug 9, 2011·0 cites·12 claims
- 2142US2023370058A1Random number generator with fd-soi lvt double-gate transistors polarised in the fbb modeCOMMISSARIAT ENERGIE ATOMIQUE·Filed 2023·Application pending·0 cites
- 2241US9437474B2Method for fabricating microelectronic devices with isolation trenches partially formed under active regionsGRENOUILLET LAURENT·Filed 2012·Granted Sep 6, 2016·0 cites·12 claims
- 2341US9437475B2Method for fabricating microelectronic devices with isolation trenches partially formed under active regionsCOMMISSARIAT ENERGIE ATOMIQUE·Filed 2012·Granted Sep 6, 2016·0 cites·15 claims
- 2441US7420253B2Three-gate transistor structureST MICROELECTRONICS CROLLES 2·Filed 2006·Granted Sep 2, 2008·0 cites·24 claims
- 2538US8652583B2Method for producing a three-dimensionally controlled surface coating in a cavityWACQUEZ ROMAIN·Filed 2010·Granted Feb 18, 2014·0 cites·12 claims
- 2637US10355207B2Method for forming a non-volatile memory cell, non-volatile memory cell formed according to said method and microelectronic device comprising such memory cellsCOMMISSARIAT ENERGIE ATOMIQUE·Filed 2018·Granted Jul 16, 2019·0 cites·13 claims
- 2736US2019172526A1Sram memory having a fast clearCOMMISSARIAT ENERGIE ATOMIQUE·Filed 2018·Application pending·0 cites
Join the waitlist — get patent alerts
Get an alert when Romain Wacquez files or is granted a new patent.
We store only your email — no account needed. See our privacy policy.
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →