Inventor · disambiguated record
Robert W. Wisniewski
Also filed as: WISNIEWSKI ROBERT · WISNIEWSKI ROBERT W
20 granted patents·10 pending applications·157 citations·filing 2006–2025
94Inventor score
Top patents by PatentIndex Score
30 records- 0195US7913041B2Cache reconfiguration based on analyzing one or more characteristics of run-time performance data or software hintIBM·Filed 2008·Granted Mar 22, 2011·38 cites·16 claims
- 0290US7634642B2Mechanism to save and restore cache and translation trace for fast context switchIBM·Filed 2006·Granted Dec 15, 2009·23 cites·21 claims
- 0388US7844778B2Intelligent cache replacement mechanism with varying and adaptive temporal residency requirementsIBM·Filed 2006·Granted Nov 30, 2010·19 cites·22 claims
- 0487US8495318B2Memory page management in a tiered memory systemTREMAINE ROBERT B·Filed 2010·Granted Jul 23, 2013·11 cites·24 claims
- 0587US8140764B2System for reconfiguring cache memory having an access bit associated with a sector of a lower-level cache memory and a granularity bit associated with a sector of a higher-level cache memorySHEN XIAOWEI·Filed 2011·Granted Mar 20, 2012·9 cites·3 claims
- 0681US8051276B2Operating system thread scheduling for optimal heat dissipationIBM·Filed 2006·Granted Nov 1, 2011·11 cites·19 claims
- 0776US8595463B2Memory architecture with policy based data storageTREMAINE ROBERT B·Filed 2010·Granted Nov 26, 2013·4 cites·20 claims
- 0875US8806177B2Prefetch engine based translation prefetchingKRIEGER ORRAN Y·Filed 2006·Granted Aug 12, 2014·8 cites·20 claims
- 0975US7895392B2Color-based cache monitoringIBM·Filed 2007·Granted Feb 22, 2011·7 cites·19 claims
- 1074US7574562B2Latency-aware thread scheduling in non-uniform cache architecture systemsIBM·Filed 2006·Granted Aug 11, 2009·6 cites·3 claims
- 1173US8671248B2Architecture support of memory access coloringSHEN XIAOWEI·Filed 2007·Granted Mar 11, 2014·6 cites·18 claims
- 1272US8869153B2Quality of service scheduling for simultaneous multi-threaded processorsKRIEGER ORRAN Y·Filed 2008·Granted Oct 21, 2014·5 cites·19 claims
- 1369US8838944B2Fast concurrent array-based stacks, queues and deques using fetch-and-increment-bounded, fetch-and-decrement-bounded and store-on-twin synchronization primitivesCHEN DONG·Filed 2009·Granted Sep 16, 2014·5 cites·13 claims
- 1465US8799581B2Cache coherence monitoring and feedbackSHEN XIAOWEI·Filed 2007·Granted Aug 5, 2014·3 cites·17 claims
- 1564US12475031B2Very large address space using extended page tablesSAMSUNG ELECTRONICS CO LTD·Filed 2024·Granted Nov 18, 2025·0 cites·20 claims
- 1663US7467280B2Method for reconfiguring cache memory based on at least analysis of heat generated during runtime, at least by associating an access bit with a cache line and associating a granularity bit with a cache line in level-2 cacheIBM·Filed 2006·Granted Dec 16, 2008·2 cites·1 claims
- 1752US2025321781A1Entangled threadsSAMSUNG ELECTRONICS CO LTD·Filed 2024·Application pending·0 cites
- 1850US2024311316A1Systems, methods, and apparatus for remote memory access by nodesSAMSUNG ELECTRONICS CO LTD·Filed 2023·Application pending·0 cites
- 1950US2024330201A1Address translation in a multi-node computing systemSAMSUNG ELECTRONICS CO LTD·Filed 2023·Application pending·0 cites
- 2050US2008022283A1Quality of service scheduling for simultaneous multi-threaded processorsIBM·Filed 2006·Application pending·0 cites
- 2149US2024311315A1Systems and methods for computing with multiple nodesSAMSUNG ELECTRONICS CO LTD·Filed 2023·Application pending·0 cites
- 2249US2024311308A1Systems and methods for computing with multiple nodesSAMSUNG ELECTRONICS CO LTD·Filed 2023·Application pending·0 cites
- 2348US12248808B2Methods and apparatus for task relocation based on memory access patternsINTEL CORP·Filed 2021·Granted Mar 11, 2025·0 cites·19 claims
- 2448US2025139007A1Systems and methods for computing with multiple nodesSAMSUNG ELECTRONICS CO LTD·Filed 2025·Application pending·0 cites
- 2548US2025139010A1Systems and methods for computing with multiple nodesSAMSUNG ELECTRONICS CO LTD·Filed 2025·Application pending·0 cites
- 2648US2025139012A1Systems and methods for computing with multiple nodesSAMSUNG ELECTRONICS CO LTD·Filed 2025·Application pending·0 cites
- 2747US2024311180A1Mechanism to migrate threads across operating systems in a distributed memory systemSAMSUNG ELECTRONICS CO LTD·Filed 2023·Application pending·0 cites
- 2844US8495649B2Scheduling threads having complementary functional unit usage on SMT processorsKRIEGER ORRAN Y·Filed 2006·Granted Jul 23, 2013·0 cites·20 claims
- 2941US9733995B2Scalable synchronization mechanism for distributed memoryCOLE CLEMENT T·Filed 2014·Granted Aug 15, 2017·0 cites·26 claims
- 3037US8543722B2Message passing with queues and channelsDOZSA GABOR J·Filed 2010·Granted Sep 24, 2013·0 cites·24 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →