Inventor · disambiguated record
Ruchira Sasanka
Also filed as: SASANKA RUCHIRA
21 granted patents·58 citations·filing 2010–2021
93Inventor score
Technology areasG06F
Top patents by PatentIndex Score
21 records- 0192US10162758B2Opportunistic increase of ways in memory-side cacheINTEL CORP·Filed 2016·Granted Dec 25, 2018·9 cites·23 claims
- 0287US9189233B2Systems, apparatuses, and methods for a hardware and software system to automatically decompose a program to multiple parallel threadsSASANKA RUCHIRA·Filed 2012·Granted Nov 17, 2015·13 cites·16 claims
- 0386US10725755B2Systems, apparatuses, and methods for a hardware and software system to automatically decompose a program to multiple parallel threadsINTEL CORP·Filed 2017·Granted Jul 28, 2020·4 cites·17 claims
- 0481US9880842B2Using control flow data structures to direct and track instruction executionINTEL CORP·Filed 2013·Granted Jan 30, 2018·7 cites·23 claims
- 0579US9672019B2Systems, apparatuses, and methods for a hardware and software system to automatically decompose a program to multiple parallel threadsSAGER DAVID J·Filed 2010·Granted Jun 6, 2017·6 cites·18 claims
- 0678US9904555B2Method, apparatus, system for continuous automatic tuning of code regionsINTEL CORP·Filed 2017·Granted Feb 27, 2018·2 cites·18 claims
- 0778US9772678B2Utilization of processor capacity at low operating frequenciesINTEL CORP·Filed 2016·Granted Sep 26, 2017·2 cites·17 claims
- 0875US9323528B2Method, apparatus, system creating, executing and terminating mini-threadsSASANKA RUCHIRA·Filed 2012·Granted Apr 26, 2016·4 cites·31 claims
- 0974US10901899B2Reducing conflicts in direct mapped cachesINTEL CORP·Filed 2019·Granted Jan 26, 2021·1 cites·20 claims
- 1071US10296457B2Reducing conflicts in direct mapped cachesINTEL CORP·Filed 2017·Granted May 21, 2019·1 cites·18 claims
- 1171US9424042B2System, apparatus and method for translating vector instructionsSASANKA RUCHIRA·Filed 2011·Granted Aug 23, 2016·3 cites·18 claims
- 1270US9558006B2Continuous automatic tuning of code regionsINTEL CORP·Filed 2012·Granted Jan 31, 2017·2 cites·22 claims
- 1366US10152421B2Instruction and logic for cache control operationsINTEL CORP·Filed 2015·Granted Dec 11, 2018·1 cites·17 claims
- 1464US9811464B2Apparatus and method for considering spatial locality in loading data elements for executionINTEL CORP·Filed 2014·Granted Nov 7, 2017·1 cites·14 claims
- 1564US9256276B2Utilization of processor capacity at low operating frequenciesINTEL CORP·Filed 2013·Granted Feb 9, 2016·1 cites·20 claims
- 1661US9170789B2Analyzing potential benefits of vectorizationINTEL CORP·Filed 2013·Granted Oct 27, 2015·1 cites·17 claims
- 1760US10599573B2Opportunistic increase of ways in memory-side cacheINTEL CORP·Filed 2018·Granted Mar 24, 2020·0 cites·20 claims
- 1858US12124371B2Apparatus and method to reduce bandwidth and latency overheads of probabilistic cachesINTEL CORP·Filed 2021·Granted Oct 22, 2024·0 cites·40 claims
- 1954US9361234B2Utilization of processor capacity at low operating frequenciesINTEL CORP·Filed 2015·Granted Jun 7, 2016·0 cites·20 claims
- 2043US10684833B2Post-compile cache blocking analyzerINTEL CORP·Filed 2018·Granted Jun 16, 2020·0 cites·25 claims
- 2142US10379827B2Automatic identification and generation of non-temporal store and load operations in a dynamic optimization environmentINTEL CORP·Filed 2016·Granted Aug 13, 2019·0 cites·19 claims
Join the waitlist — get patent alerts
Get an alert when Ruchira Sasanka files or is granted a new patent.
We store only your email — no account needed. See our privacy policy.
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →