Inventor · disambiguated record
S. Brandon Keller
Also filed as: KELLER S B · KELLER S BRANDON
14 granted patents·23 pending applications·65 citations·filing 2001–2005
89Inventor score
Top patents by PatentIndex Score
37 records- 0180US7124380B2System and method for controlling analysis of multiple instantiations of circuits in hierarchical VLSI circuit designsHEWLETT PACKARD DEVELOPMENT CO·Filed 2004·Granted Oct 17, 2006·31 cites·27 claims
- 0261US7143374B1System and method for achieving analysis capacity for circuit analysis toolsHEWLETT PACKARD DEVELOPMENT CO·Filed 2005·Granted Nov 28, 2006·2 cites·9 claims
- 0361US7086019B2Systems and methods for determining activity factors of a circuit designHEWLETT PACKARD DEVELOPMENT CO·Filed 2003·Granted Aug 1, 2006·8 cites·18 claims
- 0460US7073152B2System and method for determining a highest level signal name in a hierarchical VLSI designHEWLETT PACKARD DEVELOPMENT CO·Filed 2003·Granted Jul 4, 2006·8 cites·15 claims
- 0557US7134107B1System and method for determining detail of analysis in a circuit designHEWLETT PACKARD DEVELOPMENT CO·Filed 2004·Granted Nov 7, 2006·6 cites·16 claims
- 0652US6957367B2System and method for controlling activity of temporary files in a computer systemHEWLETT PACKARD DEVELOPMENT CO·Filed 2002·Granted Oct 18, 2005·3 cites·21 claims
- 0750US6550040B1Method and system for identifying dynamic NAND or NOR gates from a netlistHEWLETT PACKARD DEVELOPMENT CO·Filed 2001·Granted Apr 15, 2003·2 cites·11 claims
- 0849US7124393B1System and method for processing configuration informationHEWLETT PACKARD DEVELOPMENT CO·Filed 2004·Granted Oct 17, 2006·1 cites·18 claims
- 0949US7058908B2Systems and methods utilizing fast analysis information during detailed analysis of a circuit designHEWLETT PACKARD DEVELOPMENT CO·Filed 2003·Granted Jun 6, 2006·1 cites·20 claims
- 1049US7047507B2System and method for determining wire capacitance for a VLSI circuitHEWLETT PACKARD DEVELOPMENT CO·Filed 2003·Granted May 16, 2006·1 cites·21 claims
- 1149US7032206B2System and method for iteratively traversing a hierarchical circuit designHEWLETT PACKARD DEVELOPMENT CO·Filed 2003·Granted Apr 18, 2006·1 cites·20 claims
- 1248US6637012B2Method and system for identifying FETs implemented in a predefined logic equationHEWLETT PACKARD DEVELOPMENT CO·Filed 2001·Granted Oct 21, 2003·1 cites·20 claims
- 1344US7062727B2Computer aided design systems and methods with reduced memory utilizationHEWLETT PACKARD DEVELOPMENT CO·Filed 2003·Granted Jun 13, 2006·0 cites·22 claims
- 1443US7076752B2System and method for determining unmatched design elements in a computer-automated designHEWLETT PACKARD DEVELOPMENT CO·Filed 2003·Granted Jul 11, 2006·0 cites·15 claims
- 1543US2005210430A1System and method to optimize logical configuration relationships in VLSI circuit analysis toolsKELLER S B·Filed 2004·Application pending·0 cites
- 1643US2005210427A1System and method for facilitating efficient application of logical configuration information in VLSI circuit analysis toolsKELLER S B·Filed 2004·Application pending·0 cites
- 1743US2005210426A1System and method to prioritize and selectively apply configuration information for VLSI circuit analysis toolsKELLER S B·Filed 2004·Application pending·0 cites
- 1843US2005210429A1System and method to limit runtime of VLSI circuit analysis tools for complex electronic circuitsKELLER S B·Filed 2004·Application pending·0 cites
- 1943US2005210428A1System and method for flattening hierarchical designs in VLSI circuit analysis toolsKELLER S B·Filed 2004·Application pending·0 cites
- 2042US2005050483A1System and method analyzing design elements in computer aided design toolsFiled 2003·Application pending·0 cites
- 2142US2005050482A1System and method for determining applicable configuration information for use in analysis of a computer aided designFiled 2003·Application pending·0 cites
- 2242US2005050492A1Systems and methods for performing circuit analysis on a circuit designFiled 2003·Application pending·0 cites
- 2342US2005050506A1System and method for determining connectivity of nets in a hierarchical circuit designFiled 2003·Application pending·0 cites
- 2442US2005050485A1Systems and methods for identifying data sources associated with a circuit designFiled 2003·Application pending·0 cites
- 2542US2005050503A1Systems and methods for establishing data model consistency of computer aided design toolsFiled 2003·Application pending·0 cites
- 2641US2004216130A1Method for saving and restoring data in software objectsFiled 2002·Application pending·0 cites
- 2741US2003145065A1Generating a list of document addresses on a local networkFiled 2002·Application pending·0 cites
- 2841US2003145046A1Generating a list of addresses on a proxy serverFiled 2002·Application pending·0 cites
- 2940US2004078724A1Event processing systemFiled 2002·Application pending·0 cites
- 3040US2003140042A1System and method for providing pages with a common appearance at a network-based siteFiled 2002·Application pending·0 cites
- 3140US2004201631A1Generating a list of addresses in an index pageFiled 2002·Application pending·0 cites
- 3240US2003145087A1Generating a list of addresses in a serverFiled 2002·Application pending·0 cites
- 3340US2003145112A1Assisted entering of addressesFiled 2002·Application pending·0 cites
- 3440US2003106030A1Method and program product for compressing an electronic circuit modelFiled 2001·Application pending·0 cites
- 3539US2002111784A1Method of suggesting configuration commands based on E-CAD tool outputFiled 2001·Application pending·0 cites
- 3639US2003229612A1Circuit design duplication systemFiled 2002·Application pending·0 cites
- 3738US2003101198A1Method and system for generating a configuration database file based on data files of ECAD toolsFiled 2001·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →