Inventor · disambiguated record
Sanjive Agarwala
Also filed as: AGARWALA SANJIVE
31 granted patents·1 pending application·958 citations·filing 1992–2011
98Inventor score
Top patents by PatentIndex Score
32 records- 0197US6594713B1Hub interface unit and application unit interfaces for expanded direct memory access processorTEXAS INSTRUMENTS INC·Filed 2000·Granted Jul 15, 2003·200 cites·27 claims
- 0295US6606686B1Unified memory system architecture including cache and directly addressable static random access memoryTEXAS INSTRUMENTS INC·Filed 2000·Granted Aug 12, 2003·131 cites·20 claims
- 0390US6408345B1Superscalar memory transfer controller in multilevel memory organizationTEXAS INSTRUMENTS INC·Filed 2000·Granted Jun 18, 2002·73 cites·10 claims
- 0487US8904115B2Cache with multiple access pipelinesCHACHAD ABHIJEET ASHOK·Filed 2011·Granted Dec 2, 2014·4 cites·2 claims
- 0587US6694385B1Configuration bus reconfigurable/reprogrammable interface for expanded direct memory access processorTEXAS INSTRUMENTS INC·Filed 2000·Granted Feb 17, 2004·50 cites·17 claims
- 0685US6665767B1Programmer initiated cache block operationsTEXAS INSTRUMENTS INC·Filed 2000·Granted Dec 16, 2003·41 cites·16 claims
- 0784US6868087B1Request queue manager in transfer controller with hub and portsTEXAS INSTRUMENTS INC·Filed 2000·Granted Mar 15, 2005·44 cites·19 claims
- 0884US6681270B1Effective channel priority processing for transfer controller with hub and portsTEXAS INSTRUMENTS INC·Filed 2000·Granted Jan 20, 2004·39 cites·10 claims
- 0982US7325178B2Programmable built in self test of memoryTEXAS INSTRUMENTS INC·Filed 2004·Granted Jan 29, 2008·30 cites·5 claims
- 1082US6446241B1Automated method for testing cacheTEXAS INSTRUMENTS INC·Filed 2000·Granted Sep 3, 2002·34 cites·3 claims
- 1181US6594711B1Method and apparatus for operating one or more caches in conjunction with direct memory access controllerTEXAS INSTRUMENTS INC·Filed 2000·Granted Jul 15, 2003·34 cites·9 claims
- 1281US6535958B1Multilevel cache system coherence with memory selectively configured as cache or direct access memory and direct memory accessTEXAS INSTRUMENTS INC·Filed 2000·Granted Mar 18, 2003·34 cites·8 claims
- 1378US6484237B1Unified multilevel memory system architecture which supports both cache and addressable SRAMTEXAS INSTRUMENTS INC·Filed 2000·Granted Nov 19, 2002·27 cites·5 claims
- 1477US7577774B2Independent source read and destination write enhanced DMATEXAS INSTRUMENTS INC·Filed 2005·Granted Aug 18, 2009·9 cites·4 claims
- 1574US6658503B1Parallel transfer size calculation and annulment determination in transfer controller with hub and portsTEXAS INSTRUMENTS INC·Filed 2000·Granted Dec 2, 2003·20 cites·4 claims
- 1673US6009516APipelined microprocessor with efficient self-modifying code detection and handlingTEXAS INSTRUMENTS INC·Filed 1997·Granted Dec 28, 1999·68 cites·21 claims
- 1771US7095671B2Electrical fuse control of memory slowdownTEXAS INSTRUMENTS INC·Filed 2005·Granted Aug 22, 2006·7 cites·9 claims
- 1864US7716388B2Command re-ordering in hub interface unit based on priorityTEXAS INSTRUMENTS INC·Filed 2005·Granted May 11, 2010·4 cites·7 claims
- 1964US6622181B1Timing window elimination in self-modifying direct memory access processorsTEXAS INSTRUMENTS INC·Filed 2000·Granted Sep 16, 2003·10 cites·6 claims
- 2061US6654819B1External direct memory access processor interface to centralized transaction processorTEXAS INSTRUMENTS INC·Filed 2000·Granted Nov 25, 2003·8 cites·16 claims
- 2160US7603487B2Hardware configurable hub interface unitTEXAS INSTRUMENTS INC·Filed 2005·Granted Oct 13, 2009·3 cites·14 claims
- 2256US7047284B1Transfer request bus node for transfer controller with hub and portsTEXAS INSTRUMENTS INC·Filed 2000·Granted May 16, 2006·5 cites·10 claims
- 2356US5270955AMethod of detecting arithmetic or logical computation resultTEXAS INSTRUMENTS INC·Filed 1992·Granted Dec 14, 1993·21 cites·33 claims
- 2452US6954468B1Write allocation counter for transfer controller with hub and portsTEXAS INSTRUMENTS INC·Filed 2000·Granted Oct 11, 2005·2 cites·14 claims
- 2549US6928011B2Electrical fuse control of memory slowdownTEXAS INSTRUMENTS INC·Filed 2003·Granted Aug 9, 2005·5 cites·18 claims
- 2649US5629859AMethod for timing-directed circuit optimizationsTEXAS INSTRUMENTS INC·Filed 1994·Granted May 13, 1997·19 cites·5 claims
- 2749US5600583ACircuit and method for detecting if a sum of two multidigit numbers equals a third multidigit number prior to availability of the sumTEXAS INSTRUMENTS INC·Filed 1995·Granted Feb 4, 1997·18 cites·9 claims
- 2842US6985982B2Active ports in a transfer controller with hub and portsTEXAS INSTRUMENTS INC·Filed 2001·Granted Jan 10, 2006·0 cites·15 claims
- 2941US7673076B2Concurrent read response acknowledge enhanced direct memory access unitTEXAS INSTRUMENTS INC·Filed 2005·Granted Mar 2, 2010·0 cites·2 claims
- 3040US5508950ACircuit and method for detecting if a sum of two multibit numbers equals a third multibit constant number prior to availability of the sumTEXAS INSTRUMENTS INC·Filed 1993·Granted Apr 16, 1996·9 cites·5 claims
- 3138US2006259665A1Configurable multiple write-enhanced direct memory access unitAGARWALA SANJIVE·Filed 2005·Application pending·0 cites
- 3236US5813028ACache read miss request invalidation prevention methodTEXAS INSTRUMENTS INC·Filed 1996·Granted Sep 22, 1998·9 cites·1 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →