Inventor · disambiguated record
Sadok Aouini
Also filed as: AOUINI SADOK
52 granted patents·2 pending applications·260 citations·filing 2008–2025
98Inventor score
Top patents by PatentIndex Score
54 records- 0196US10985900B1Estimating clock phase error based on channel conditionsCIENA CORP·Filed 2020·Granted Apr 20, 2021·8 cites·20 claims
- 0296US10903841B1Apparatus and methods for high frequency clock generationCIENA CORP·Filed 2020·Granted Jan 26, 2021·14 cites·20 claims
- 0396US10715155B1Apparatus and methods for digital phase locked loop with analog proportional control functionCIENA CORP·Filed 2019·Granted Jul 14, 2020·16 cites·20 claims
- 0495US10965300B1High bandwidth under-sampled successive approximation register analog to digital converter with nonlinearity minimizationCIENA CORP·Filed 2020·Granted Mar 30, 2021·10 cites·20 claims
- 0595US10931292B1High resolution successive approximation register analog to digital converter with factoring and background clock calibrationCIENA CORP·Filed 2020·Granted Feb 23, 2021·10 cites·20 claims
- 0695US10848164B1Apparatus and methods for digital fractional phase locked loop with a current mode low pass filterCIENA CORP·Filed 2020·Granted Nov 24, 2020·10 cites·17 claims
- 0795US10063367B1Optical clock recovery using feedback phase rotator with non-linear compensationCIENA CORP·Filed 2017·Granted Aug 28, 2018·16 cites·18 claims
- 0894US10979059B1Successive approximation register analog to digital converter based phase-locked loop with programmable rangeCIENA CORP·Filed 2020·Granted Apr 13, 2021·12 cites·20 claims
- 0993US10826514B1Noise-shaping enhanced gated ring oscillator based analog-to-digital convertersCIENA CORP·Filed 2019·Granted Nov 3, 2020·13 cites·20 claims
- 1093US10715169B1Coarse-fine gain-tracking loop and method of operatingCIENA CORP·Filed 2019·Granted Jul 14, 2020·14 cites·20 claims
- 1193US10680585B2Techniques and circuits for time-interleaved injection locked voltage controlled oscillators with jitter accumulation resetCIENA CORP·Filed 2018·Granted Jun 9, 2020·6 cites·17 claims
- 1293US10516403B1High-order phase tracking loop with segmented proportional and integral controlsCIENA CORP·Filed 2019·Granted Dec 24, 2019·10 cites·20 claims
- 1393US10425099B1Extremely-fine resolution sub-ranging current mode Digital-Analog-Converter using Sigma-Delta modulatorsCIENA CORP·Filed 2018·Granted Sep 24, 2019·17 cites·20 claims
- 1493US10243671B1Clock recovery circuits, systems and implementation for increased optical channel densityCIENA CORP·Filed 2017·Granted Mar 26, 2019·13 cites·17 claims
- 1592US11595047B1Apparatus and methods for a phase frequency detector with a wide operational rangeCIENA CORP·Filed 2022·Granted Feb 28, 2023·4 cites·20 claims
- 1692US10320374B2Fine resolution high speed linear delay elementCIENA CORP·Filed 2017·Granted Jun 11, 2019·9 cites·20 claims
- 1791US11171664B1Digitally enhanced digital-to-analog converter resolutionCIENA CORP·Filed 2020·Granted Nov 9, 2021·3 cites·20 claims
- 1889US10805064B1Built-in jitter loading and state of polarization generation to characterize optical transceiversCIENA CORP·Filed 2019·Granted Oct 13, 2020·7 cites·18 claims
- 1989US10749536B1High-order phase tracking loop with segmented proportional and integral controlsCIENA CORP·Filed 2019·Granted Aug 18, 2020·5 cites·19 claims
- 2088US10187197B2Optical clock recovery using feedback phase rotator with non-linear compensationCIENA CORP·Filed 2018·Granted Jan 22, 2019·6 cites·20 claims
- 2187US11463093B1Reducing non-linearities of a phase rotatorCIENA CORP·Filed 2021·Granted Oct 4, 2022·2 cites·20 claims
- 2287US10855380B2Clock recovery circuits, systems and implementation for increased optical channel densityCIENA CORP·Filed 2019·Granted Dec 1, 2020·5 cites·19 claims
- 2385US11770126B2Noise-shaping enhanced gated ring oscillator based analog-to-digital convertersCIENA CORP·Filed 2020·Granted Sep 26, 2023·2 cites·20 claims
- 2485US10536303B1Quarter-rate charge-steering decision feedback equalizer (DFE) tapsPIKE JACOB·Filed 2018·Granted Jan 14, 2020·8 cites·20 claims
- 2584US10554453B1Quarter-rate charge-steering decision feedback equalizer (DFE)PARVIZI MAHDI·Filed 2019·Granted Feb 4, 2020·8 cites·20 claims
- 2684US8855215B2Phase/frequency synthesis using periodic sigma-delta modulated bit-stream techniquesROBERTS GORDON·Filed 2011·Granted Oct 7, 2014·12 cites·7 claims
- 2783US11233519B1Phase skipping technique for high-speed, high-phase number delay locked loopCIENA CORP·Filed 2021·Granted Jan 25, 2022·3 cites·16 claims
- 2883US11012081B2Apparatus and methods for digital phase locked loop with analog proportional control functionCIENA CORP·Filed 2020·Granted May 18, 2021·2 cites·18 claims
- 2979US12395177B2Reducing non-linearities of a phase rotatorCIENA CORP·Filed 2024·Granted Aug 19, 2025·0 cites·20 claims
- 3078US11201723B1Highly linear phase rotators with continuous rotationCIENA CORP·Filed 2020·Granted Dec 14, 2021·1 cites·19 claims
- 3178US10281523B2Techniques and circuits for on-chip jitter and phase noise measurement in a digital test environmentCIENA CORP·Filed 2017·Granted May 7, 2019·5 cites·20 claims
- 3275US9787466B2High order hybrid phase locked loop with digital scheme for jitter suppressionAOUINI SADOK·Filed 2016·Granted Oct 10, 2017·4 cites·20 claims
- 3373US2025216604A1Resonant device improvement in PICs using spare devices to reduce power requirementsCIENA CORP·Filed 2025·Application pending·0 cites
- 3470US12265252B2Resonant device improvement in PICs using spare devices to reduce power requirementsCIENA CORP·Filed 2021·Granted Apr 1, 2025·0 cites·14 claims
- 3570US12034448B2Reducing non-linearities of a phase rotatorCIENA CORP·Filed 2022·Granted Jul 9, 2024·0 cites·20 claims
- 3670US2025070789A1Method and apparatus for clock and data alignment that reduces power consumptionCIENA CORP·Filed 2024·Application pending·0 cites
- 3766US8849882B2Generation of an analog Gaussian noise signal having predetermined characteristicsAOUINI SADOK·Filed 2008·Granted Sep 30, 2014·5 cites·4 claims
- 3865US12176908B2Method and apparatus for clock and data alignment that reduces power consumptionCIENA CORP·Filed 2022·Granted Dec 24, 2024·0 cites·20 claims
- 3963US12308854B2Digitally enhanced digital-to-analog converter resolutionCIENA CORP·Filed 2021·Granted May 20, 2025·0 cites·20 claims
- 4062US11502695B2High bandwidth under-sampled successive approximation register analog to digital converter with nonlinearity minimizationCIENA CORP·Filed 2021·Granted Nov 15, 2022·0 cites·20 claims
- 4161US12289391B2Low latency data handoff using phase rotation and clock gappingCIENA CORP·Filed 2022·Granted Apr 29, 2025·0 cites·20 claims
- 4261US12034460B2Apparatus and method for Sigma-Delta modulator quantization noise cancellationCIENA CORP·Filed 2022·Granted Jul 9, 2024·0 cites·16 claims
- 4361US11349486B1High-order phase tracking loop with segmented proportional and integral controlsCIENA CORP·Filed 2020·Granted May 31, 2022·0 cites·20 claims
- 4460US12489451B2Multiphase clock generatorCIENA CORP·Filed 2023·Granted Dec 2, 2025·0 cites·20 claims
- 4560US11245401B2Apparatus and methods for high frequency clock generationCIENA CORP·Filed 2020·Granted Feb 8, 2022·0 cites·20 claims
- 4659US11561570B2Apparatus and methods for low power frequency clock generation and distributionCIENA CORP·Filed 2020·Granted Jan 24, 2023·0 cites·20 claims
- 4758US11818242B2Built-in jitter loading and state of polarization generation to characterize optical transceiversCIENA CORP·Filed 2020·Granted Nov 14, 2023·0 cites·20 claims
- 4856US11218155B2Apparatus and methods for digital fractional phase locked loop with a current mode low pass filterCIENA CORP·Filed 2020·Granted Jan 4, 2022·0 cites·17 claims
- 4955US11770203B2Matching transmitters with receivers for making network-level assignmentsCIENA CORP·Filed 2021·Granted Sep 26, 2023·0 cites·19 claims
- 5054US11196438B1High resolution analog to digital converter with factoring and background clock calibrationCIENA CORP·Filed 2021·Granted Dec 7, 2021·0 cites·20 claims
Showing the top 50 of 54 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →