Inventor · disambiguated record
Saul Barajas
Also filed as: BARAJAS SAUL
17 granted patents·380 citations·filing 1990–1997
95Inventor score
Files withUNISYS CORP17
Top patents by PatentIndex Score
17 records- 0172US5598551ACache invalidation sequence system utilizing odd and even invalidation queues with shorter invalidation cyclesUNISYS CORP·Filed 1996·Granted Jan 28, 1997·72 cites·5 claims
- 0272US5553263ACache memory system with fault tolerance having concurrently operational cache controllers processing disjoint groups of memoryUNISYS CORP·Filed 1993·Granted Sep 3, 1996·60 cites·15 claims
- 0372US5506967AStorage queue with adjustable level thresholds for cache invalidation systems in cache oriented computer architecturesUNISYS CORP·Filed 1993·Granted Apr 9, 1996·59 cites·10 claims
- 0470US5086427AClocked logic circuitry preventing double driving on shared data busUNISYS CORP·Filed 1990·Granted Feb 4, 1992·36 cites·2 claims
- 0560US5146596AMultiprocessor multifunction arbitration system with two levels of bus access including priority and normal requestsUNISYS CORP·Filed 1990·Granted Sep 8, 1992·37 cites·3 claims
- 0659US5561773AProgrammable, multi-purpose virtual pin multiplierUNISYS CORP·Filed 1993·Granted Oct 1, 1996·14 cites·6 claims
- 0752US5459836AInter-processor communication netUNISYS CORP·Filed 1992·Granted Oct 17, 1995·25 cites·10 claims
- 0849US5087953AFlexible gate array system for combinatorial logicUNISYS CORP·Filed 1990·Granted Feb 11, 1992·9 cites·8 claims
- 0945US6070166AApparatus and method for compressing a plurality of contiguous addresses to form a compressed block address using the first address of the contiguous addresses and a block identifier bitUNISYS CORP·Filed 1997·Granted May 30, 2000·12 cites·10 claims
- 1044US5321814ASystem for optional module detection and reconfigurationUNISYS CORP·Filed 1992·Granted Jun 14, 1994·16 cites·3 claims
- 1144US5117132AFlexible utilization of general flip-flops in programmable array logicUNISYS CORP·Filed 1991·Granted May 26, 1992·7 cites·13 claims
- 1239US5689680ACache memory system and method for accessing a coincident cache with a bit-sliced architectureUNISYS CORP·Filed 1993·Granted Nov 18, 1997·9 cites·3 claims
- 1337US5418935AApparatus for preventing double drive occurrences on a common bus by delaying enablement of one driver after indication of disablement to other driver is receivedUNISYS CORP·Filed 1993·Granted May 23, 1995·9 cites·4 claims
- 1435US5553259AApparatus and method for synchronizing the simultaneous loading of cache program word addresses in dual slice registersUNISYS CORP·Filed 1995·Granted Sep 3, 1996·8 cites·5 claims
- 1535US5087839AMethod of providing flexibility and alterability in VLSI gate array chipsUNISYS CORP·Filed 1990·Granted Feb 11, 1992·6 cites·11 claims
- 1630US5642486AInvalidation queue with "bit-sliceability"UNISYS CORP·Filed 1993·Granted Jun 24, 1997·1 cites·2 claims
- 1727US5991853AMethods for accessing coincident cache with a bit-sliced architectureUNISYS CORP·Filed 1997·Granted Nov 23, 1999·0 cites·3 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →