Inventor · disambiguated record
Sailendra Chadalavada
Also filed as: CHADALAVADA SAILENDRA
7 granted patents·2 pending applications·3 citations·filing 2016–2025
73Inventor score
Files withNVIDIA CORP9
Top patents by PatentIndex Score
9 records- 0179US11867744B2Techniques for isolating interfaces while testing semiconductor devicesNVIDIA CORP·Filed 2020·Granted Jan 9, 2024·1 cites·20 claims
- 0273US2025222941A1Localized in-system testing for autonomous and semi-autonomous systems and applicationsNVIDIA CORP·Filed 2025·Application pending·0 cites
- 0372US12291219B2Asynchronous in-system testing for autonomous systems and applicationsNVIDIA CORP·Filed 2022·Granted May 6, 2025·0 cites·19 claims
- 0471US10746798B1Field adaptable in-system test mechanismsNVIDIA CORP·Filed 2019·Granted Aug 18, 2020·1 cites·18 claims
- 0566US12480990B2Technique for enabling on-die noise measurement during ate testing and ISTNVIDIA CORP·Filed 2022·Granted Nov 25, 2025·0 cites·45 claims
- 0665US10890620B2On-chip execution of in-system test utilizing a generalized test imageNVIDIA CORP·Filed 2019·Granted Jan 12, 2021·1 cites·18 claims
- 0758US10545189B2Granular dynamic test systems and methodsNVIDIA CORP·Filed 2016·Granted Jan 28, 2020·0 cites·25 claims
- 0849US11668750B2Performing testing utilizing staggered clocksNVIDIA CORP·Filed 2021·Granted Jun 6, 2023·0 cites·18 claims
- 0939US2022365857A1Runtime in-system testingNVIDIA CORP·Filed 2021·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →